Analog layout Engineer

Programmers.io; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Programmers.io in Austin, TX seeks an experienced analog/mixed-signal layout engineer to craft robust layouts meeting tight matching, area and power constraints.

You will review floorplans with circuit designers, run extensive verification tools, and use Cadence Virtuoso, Mentor Graphics, and Calibre to deliver high-quality, low-noise analog blocks.

Qualifications

• Experience in analog/mixed-signal IP layout, including SERDES PHYs, ADCs, DACs, and power/ground structures.
• Ability to work with circuit designers and layout leads to plan and trade off layouts.
• Strong understanding of floorplans and complex circuits with designers.
• Proficiency in using CAD tools to deliver robust, well-matched layouts.

Responsibilities

• Review and analyze floor-plans and complex circuits with the circuit designer.
• Run complete set of design verification tools available.
• Collaborate with layout lead to plan/schedule work and negotiate layout trade-offs as needed.
• Develop well-matched, low-noise, low-power analog blocks and ESD structures.

Skills

Analog layout

Mixed-signal layout

IP design blocks

Noise optimization

Low power design

Mentor Graphics

Cadence Virtuoso

Calibre DRC/ER C/LVS

Floorplan analysis

IR drop awareness

RC delay management

Tools

Cadence Virtuoso

Mentor Graphics

Calibre DRC

LVS verification tools

Job description

• :Knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.
• )Experienced working with the circuit designer or layout lead to plan/schedule work and negotiate any layout trade-offs as neede
• dReviewing and analyzing floor-plans and complex circuits with circuit designer
• sRunning complete set of design verification tools availabl
• eGreat understanding and experience using advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirement
• sExperienced in crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc
• .Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitanc
• eMust recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problem
• sHigh level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., report
• sKnowledge of CADENCE Virtuoso and MENTOR GRAPHICS layout tool