Analog Layout Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

Apple Inc. is seeking an experienced Analog Layout Engineer in Beaverton, Oregon. This role involves developing layouts for analog mixed-signal circuits and operating within SOC flows. Candidates should possess over 10 years of expertise in analog design, with proficiency in tools like Cadence Virtuoso, along with strong programming skills in scripting languages.

The position emphasizes collaboration with cross-functional teams to drive innovation in SOC architectures and promotes a rich culture of diversity and inclusion.

Qualifications

• A minimum of 10 years of relevant industry experience.
• Experience with deep submicron CMOS circuits and FinFET technologies.
• Proven expertise in achieving tight matching, low noise, and low power consumption.

Responsibilities

• Craft sophisticated layouts for mixed-signal and analog circuits.
• Coordinate layout tradeoffs and run design verification tools.
• Interpret LVS, DRC, and ERC reports effectively.

Skills

Analog/mixed-signal layout design

Programming/scripting in SKILL, Perl, TCL, Shell, Python

Machine Learning and AI concepts

Ultra-high speed ADC/DAC experience

Technical understanding of IR drop, RC delay

Cadence Virtuoso

Communication skills

Education

BS in Electrical and Computer Engineering

MSEE or Ph.D. in Electrical and Computer Engineering

Tools

Cadence Innovus

Cadence Virtuoso

Job description

Description

Analog Layout engineers are pivotal in delivering Analog Mixed‑Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world‑leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed‑signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience.

Preferred Qualifications

• 10+ years of experience in analog/mixed‑signal layout design, with a focus on deep submicron CMOS circuits and at least 3+ years in FinFET technologies.
• Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python.
• Familiar with Machine Learning and AI concepts.
• Experience with ultra‑high speed ADC/DAC.
• Proven Expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption.
• Must recognize failure‑prone circuit and layout structures, have experience with analog and DFM standards, and be able to identify the best approach to solving problems.
• High Proficiency in custom and standard cell‑based floor‑planning and hierarchical layout assembly.
• Technical understanding of IR drop, RC delay, electromigration, self‑heating, and coupling capacitance.
• High Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.).
• Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager).
• Excellent communication skills and ability to work with cross‑functional teams.
• Cadence Innovus.
• PCell creation experience.
• MSEE or Ph.D. in Electrical and Computer Engineering.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.