Analog Layout Engineer

Saksoft; Cupertino (CA); On-site; USD 120,000 - 180,000; Part time

Job summary

Saksoft is seeking an Analog Layout Engineer in Cupertino, CA for a long-term contract role. You will lead the layout of analog ICs for high-speed applications in advanced CMOS FinFET technologies and oversee floor planning, routing, and top-level assembly to ensure optimal performance.

The ideal candidate brings 6+ years of analog layout experience, with deep knowledge of Cadence, Mentor, and Synopsys tools and hands-on work on transceivers, drivers, data converters, and PLLs.

Qualifications

• Minimum 6+ years of experience in analog layout design.
• Experience leading complex layout IC for high-speed applications in CMOS FinFETs (7nm and below).
• Proficiency with Cadence, Mentor, and Synopsys EDA tools.
• Experience with layout of high-performance high-speed analog mixed-signal blocks (Transceivers, CMOS drivers, DACs/PLLs).
• Experience with floor planning, block-level routing and top-level chip assembly.
• Knowledge of floor planning, layer generation, thermal-aware layout and electromigration considerations.

Responsibilities

• Lead analog layout activities at block and chip levels.
• Perform floor planning and block-level routing for high-speed ICs.
• Collaborate with design teams to optimize performance, area, and power.

Skills

Analog layout

IC layout

High-speed design

Floor planning

Top-level chip assembly

Transceivers / PLLs

Tools

Cadence

Mentor

Synopsys

Job description

Job Title: Analog Layout Engineer

Location: Cupertino, CA (on-site)

Hire Type: Contract

Duration: Long-term

Job Description

• Minimum 6+ years of experience in Analog layout design.
• Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level.
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs.
• Experience with floor planning, block level routing and top-level chip assemble.
• Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.