Principal Analog Mixed-Signal Design Engineer

SiTime; Santa Clara (CA); On-site; USD 164,800 - 226,600; Full time

Benefits offered by this job

401k plan

Health and wellness benefits including medical, dental, and vision

Time off plans

Job summary

SiTime, based in Santa Clara, California, is seeking an experienced engineer to lead the development of analog mixed-signal ICs. The role requires a strong track record in delivering high-volume production and entails supervising design work as well as collaboration across teams for DFT.

Qualified candidates should have a master's degree in Electrical Engineering, 10 years of experience, and proficiency in EDA tools. Benefits include a comprehensive health plan and competitive salary range of $164,800 – $226,600.

Qualifications

• 10 years of relevant experience or a Ph.D. with 6 years in Electrical Engineering.
• Proven track record of high-volume production of analog mixed-signal parts.
• Ability to work independently and drive solutions to complex problems.

Responsibilities

• Lead development of analog mixed-signal IC.
• Supervise and review block designer work.
• Collaboration with cross-functional teams on chip architecture for DFT.

Skills

Analog mixed-signal design

EDA tools proficiency

Communication skills

Circuit design and simulation

Education

M.Sc. in Electrical Engineering with 10+ years of experience or Ph.D. with 6+ years

Tools

Cadence Virtuoso

Spectre

Mixed-mode AMS tools

Job description

About SiTime

SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non‑silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS‑based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high‑growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Responsibilities

• Lead development of analog mixed‑signal IC and owns the top level
• Supervise and review block designer work and hold design review
• Work with cross‑functional team to architect the chip for DFT
• Closely work and support cross functional team for bench validation, qualification and final test development
• Develop analog and mixed‑signal architectures and circuits in CMOS or BiCMOS processes
• Analyze technology, architecture, circuit design, and parametric design trade‑offs to meet aggressive technical performance specifications
• Perform transistor‑level design and simulation using industry leading EDA tools
• Lead comprehensive design reviews
• Supervise Analog Circuit Physical Design Layout and edit layouts
• Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring‑up and time to production release
• Work closely with the verification team to define the verification matrix
• Have the ownership of the top‑level schematic and run all the top‑level analog simulation
• Participate in top‑level AMS verification

Qualifications & Requirements

• M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of relevant experience in Electrical Engineering
• Proof of track record of taking at least one analog‑mixed‑signal part to high‑volume production
• Proven track record at each stage of the following:
  • Circuit architecture development and technical feasibility studies
  • Writing detailed block‑level specifications and review documents
• Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional‑N PLLs, Digital PLLs, low‑noise op‑amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture
  • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed‑mode AMS tools, and Layout XL
  • Extensive knowledge of layout effects for circuit and layout design; ability to supervise layout designers
  • Extensive experience with post‑layout extraction and verifications
  • Experience with validation, characterization, qualification, and adherence to production release criteria
  • Ability to communicate and work effectively with geographically dispersed teams of mixed‑signal, digital, and verification engineers
  • Ability to work independently and drive solutions to challenging problems

Desired Characteristics & Attributes

• Strong team player

Compensation Range

The annual base salary range for this role is $164,800.00 – $226,600.00. The final offer is determined by factors such as location, experience, education, and training. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered

401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer. We treat each person fairly and do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E‑Verify program.