AI-Powered RTL Methodology Engineer

AMD

Austin (TX)

On-site

USD 120,000 - 180,000

Full time

14 days+

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Job summary

AMD in Austin is seeking an RTL Methodology Engineer to define and automate the flows that power core RTL design. You will build AI-powered tools and agentic workflows, applying LLM-based assistance, code generation, and automated analysis to accelerate design, review, and debugging across the CPU core team.

You will collaborate with Performance Modeling, Design Verification, Physical Design and Post-Silicon teams to push the silicon roadmap forward, own critical tooling, and contribute to

Qualifications

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience with Verilog/SystemVerilog in CPU/SoC/ASIC contexts.
  • Strong scripting and programming skills (Python, Go, Java, or TypeScript).

Responsibilities

  • Execute and refine RTL design methodology and tooling.
  • Develop AI-powered tools and agentic workflows for RTL design.
  • Own and advance RTL static analysis ecosystem (linting, parsers, ASTs).
  • Identify opportunities to apply AI across RTL flow and prototype.
  • Collaborate with hardware and infrastructure engineers to build RTL infrastructure.
  • Own, refine, and maintain critical RTL tools.
  • Team up with multi-disciplinary teams to unlock RTL efficiency.
  • Contribute to silicon debug and product support as needed.

Skills

Verilog/SystemVerilog
RTL development
AI tooling
Python scripting
Go/Java
Debugging
Design workflows

Education

BS/MS/PhD in EE/CE/CS

Tools

Verible
Verilator
Slang
Surelog
ASTs

Job description

AMD in Austin is seeking an RTL Methodology Engineer to define and automate the flows that power core RTL design. You will build AI-powered tools and agentic workflows, applying LLM-based assistance, code generation, and automated analysis to accelerate design, review, and debugging across the CPU core team.

You will collaborate with Performance Modeling, Design Verification, Physical Design and Post-Silicon teams to push the silicon roadmap forward, own critical tooling, and contribute to

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