AI Hardware Digital Design Engineer (RISC-V/MPU) - Hybrid

BrainChip; Laguna Hills (CA); Híbrido; USD 120 000 - 160 000; Tempo integral

Resumo da oferta

BrainChip in Laguna Hills, CA seeks a Digital Design Engineer to design and implement core compute architecture for next-generation AI hardware. This role sits on the hardware team and spans RTL, microarchitecture, verification and silicon bring-up.

You will translate product requirements into scalable designs, build processor cores including RISC-V-based architectures, and collaborate with cross-functional teams across hardware and software to ship silicon powering AI workloads.

Qualificações

• 3+ years of experience in digital design or RTL development.
• Strong understanding of modern processor and compute architectures.
• Experience with embedded MPU design, ideally RISC-V or similar.
• Proficiency in Verilog and SystemVerilog.
• Familiarity with SoC components, memory systems, and system buses such as AXI, AHB, or APB.

Responsabilidades

• Translate product requirements into scalable microarchitecture designs.
• Design and implement digital modules using RTL.
• Develop and integrate processor cores including RISC-V-based architectures.
• Contribute to CPU design including pipeline, cache, and system architecture.
• Build and debug FPGA prototypes for system-level validation.
• Run simulations at RTL and gate level to verify functionality.
• Collaborate on verification strategies and test plans.
• Work closely with cross-functional teams across hardware and software.

Conhecimentos

RTL design

Verilog/SystemVerilog

RISC-V

Debugging

Ferramentas

VCS

Verdi

Descrição da oferta de emprego

BrainChip in Laguna Hills, CA seeks a Digital Design Engineer to design and implement core compute architecture for next-generation AI hardware. This role sits on the hardware team and spans RTL, microarchitecture, verification and silicon bring-up.

You will translate product requirements into scalable designs, build processor cores including RISC-V-based architectures, and collaborate with cross-functional teams across hardware and software to ship silicon powering AI workloads.