AI-Driven PD Implementation & Signoff Architect

Altera; San Jose (CA); On-site; USD 232,000 - 341,000; Full time

Job summary

Altera is seeking a Physical Design Implementation & Signoff Lead & Architect to own and reinvent PD implementation and signoff methodology across multiple tapeouts. This senior IC role emphasizes architecture, not people management, and requires leadership in EMIR, STA, and power signoff across several process nodes.

The role sits on the senior IC ladder, offering influence over flows, standards, and quality gates while mentoring the next generation of PD engineers.

Qualifications

• Deep expertise in PD implementation and signoff across EMIR, STA, and power.
• Experience deploying PD methodologies across multiple tapeouts and process nodes.
• Strong cross-functional collaboration and communication skills.
• Experience with AI/ML-based EDA flows for productivity and quality gains.
• Mentorship of CAD engineers and methodology evangelism.

Responsibilities

• Own end-to-end PD implementation and signoff methodology across product portfolio.
• Define and improve PD flows and standards for all design teams.
• Introduce AI/ML-driven techniques for timing, power, and EMIR prediction and automation.
• Architect scalable flows to handle increasing project concurrency.
• Collaborate with foundry PDKs and technology qualification teams.
• Lead root-cause analysis and drive convergence of signoff issues.
• Mentor engineers to raise technical standards.

Skills

EMIR analysis

STA timing

Power signoff

Place-and-route

Python scripting

ML-driven design

cross-functional influence

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

Ansys RedHawk-SC

Synopsys PrimeTime

PrimePower

Cadence Innovus

Voltus

Tempus

Job description

Altera is seeking a Physical Design Implementation & Signoff Lead & Architect to own and reinvent PD implementation and signoff methodology across multiple tapeouts. This senior IC role emphasizes architecture, not people management, and requires leadership in EMIR, STA, and power signoff across several process nodes.

The role sits on the senior IC ladder, offering influence over flows, standards, and quality gates while mentoring the next generation of PD engineers.