Front-End CAD Methodology Engineer – Design/DV Interface

Apple Inc.

San Francisco (CA)

On-site

USD 216,200 - 394,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Stock programs
Relocation assistance
Tuition reimbursement
Medical and dental coverage

Job summary

Apple Inc. in the San Francisco Bay Area is seeking a Front-End CAD Methodology Engineer to design and promote scalable methodology solutions across RTL Design and DV teams.

You will leverage automation and GenAI-enabled tooling to boost engineering productivity and quality in silicon development. Collaborating with design and verification engineers, Cadence/Synopsys tool users, and cross‑functional CAD teams, you will translate complex challenges into reusable workflows that accelerate chip

Qualifications

  • Minimum of BS degree and 15+ years of relevant experience.
  • Experience with Front-End ASIC workflows.
  • Experience working with design and verification engineers to define requirements and implement solutions.
  • Experience with artificial intelligence and machine learning.

Responsibilities

  • Promote and drive robust methodology solutions across RTL Design and DV teams.
  • Leverage automations and GenAI-enabled tooling to improve productivity and quality.
  • Collaborate with CAD teams to translate complex engineering challenges into scalable, reusable solutions.

Skills

Front-End ASIC workflows
AI/ML experience
Collaboration with design/verification

Education

BS degree

Tools

Cadence tools
Synopsys tools
Python/TCL/Perl
Verilog/SystemVerilog
JSON/YAML

Job description

Front-End CAD Methodology Engineer – Design/DV Interface

San Francisco Bay Area, California, United States Hardware

Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!

Description

The Front-End CAD Methodology Engineer plays a key role in promoting and driving robust, scalable methodology solutions across RTL Design and DV teams within Apple’s HWTech organization. This role leverages advanced automations and GenAI-driven capabilities to enhance engineering productivity, improve methodology quality, and enable intelligent workflow optimization across static verification, formal verification, simulation and emulation domains. This position requires a combination of deep technical expertise, architectural vision, and technical leadership to identify high-impact opportunities, design and architect innovative solutions, including GenAI-enabled tooling, and drive adoption across a large globally distributed engineering organization. You will work closely with the different design organizations and CAD teams to translate complex engineering challenges into scalable, reusable, and forward-looking methodology solutions that accelerate silicon development and verification while maintaining the highest standards of quality and efficiency. In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups: To create, monitor, and maintain high quality flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple’s chip design efforts.

Minimum Qualifications
  • Minimum of BS degree and 15+ years of relevant experience
  • Experience with Front-End ASIC workflows
  • Experience working directly with design and verification engineers to define requirements and implement solutions
  • Experience with artificial intelligence and machine learning
Preferred Qualifications
  • Experience with Cadence or Synopsys’ static/formal/dynamic verification tools
  • Experience with Python, TCL or Perl
  • Experience with JSON or YAML
  • Knowledge in Verilog and SystemVerilog; familiarity with VHDL
  • Demonstrated experience driving large-scale software system development from specification to deployment
  • Experience in implementing new functionality to solve emerging problems or to optimize already existing methods
  • Great teammate with strong written and verbal interpersonal skills, and a service and support mentality
  • Good communications skills are required and prior customer support experience
  • MSEE/CE/CS preferred

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $216,200 and $394,000, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

FE RTL Infrastructure - CAD Engineer
FE RTL Infrastructure - CAD Engineer

Apple Inc. • Cupertino (CA)

On-site
USD 126,000 - 191,000
Comprehensive medical and dental coverage
Retirement benefits
Employee stock programs
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • San Francisco (CA)

On-site
USD 147,000 - 273,000
Comprehensive medical and dental coverage
Retirement benefits
Discounted products and services
+2
FE RTL Infrastructure - CAD Engineer
FE RTL Infrastructure - CAD Engineer

Apple Inc. • Beaverton (OR)

On-site
USD 100,000 - 130,000
Design Verification Engineer
Design Verification Engineer

Apple Inc. • Sunnyvale (CA)

On-site
USD 150,000 - 278,000
Medical and dental coverage
Stock plan eligibility
Relocation assistance
+1
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • Beaverton (OR)

On-site
USD 90,000 - 120,000
CAD Engineer – Design Verification Methodology
CAD Engineer – Design Verification Methodology

Apple Inc. • Austin (TX)

On-site
USD 90,000 - 120,000
Design Verification Engineer
Design Verification Engineer

Apple Inc. • Cupertino (CA)

On-site
USD 126,000 - 191,000
Comprehensive medical and dental coverage
Retirement benefits
Discounted products and services
+1
Design Verification Engineer
Design Verification Engineer

Apple Inc. • Waltham (MA)

On-site
USD 149,700 - 249,500
ASIC Design Engineer
ASIC Design Engineer

Apple Inc. • Cupertino (CA)

On-site
USD 180,000 - 280,000
CPU Top-Level Design Verification Engineer
CPU Top-Level Design Verification Engineer

Apple Inc. • Santa Clara (CA)

On-site
USD 129,000 - 195,000
Stock programs
Relocation assistance
Medical & dental coverage