GenAI-Driven Front-End CAD Methodology Engineer

Apple Inc.; San Francisco (CA); On-site; USD 216,200 - 394,000; Full time

Benefits offered by this job

Stock programs

Relocation assistance

Tuition reimbursement

Medical and dental coverage

Job summary

Apple Inc. in the San Francisco Bay Area is seeking a Front-End CAD Methodology Engineer to design and promote scalable methodology solutions across RTL Design and DV teams.

You will leverage automation and GenAI-enabled tooling to boost engineering productivity and quality in silicon development. Collaborating with design and verification engineers, Cadence/Synopsys tool users, and cross‑functional CAD teams, you will translate complex challenges into reusable workflows that accelerate chip

Qualifications

• Minimum of BS degree and 15+ years of relevant experience.
• Experience with Front-End ASIC workflows.
• Experience working with design and verification engineers to define requirements and implement solutions.
• Experience with artificial intelligence and machine learning.

Responsibilities

• Promote and drive robust methodology solutions across RTL Design and DV teams.
• Leverage automations and GenAI-enabled tooling to improve productivity and quality.
• Collaborate with CAD teams to translate complex engineering challenges into scalable, reusable solutions.

Skills

Front-End ASIC workflows

AI/ML experience

Collaboration with design/verification

Education

BS degree

Tools

Cadence tools

Synopsys tools

Python/TCL/Perl

Verilog/SystemVerilog

JSON/YAML

Job description

Apple Inc. in the San Francisco Bay Area is seeking a Front-End CAD Methodology Engineer to design and promote scalable methodology solutions across RTL Design and DV teams.

You will leverage automation and GenAI-enabled tooling to boost engineering productivity and quality in silicon development. Collaborating with design and verification engineers, Cadence/Synopsys tool users, and cross‑functional CAD teams, you will translate complex challenges into reusable workflows that accelerate chip