AI-Driven Chip Design Infrastructure Engineer

Ricursive; Palo Alto (CA); On-site; USD 190,000 - 235,000; Full time

Job summary

Ricrecursive Intelligence in the Palo Alto area is hiring a Software Engineer to build and scale the end-to-end RTL-to-GDSII flow. You will work across the design stack, running complex chip designs at scale and improving how we evaluate and iterate on designs within production constraints.

You will automate design analysis, integrate EDA tools, and collaborate with in‑house experts to deliver faster feedback, tighter PPA, and robust engineering workflows that support cutting‑edge AI hardware

Qualifications

• Bachelor’s degree in CS, EE, or related field.
• Strong programming in Python, C++, or Java.
• Understanding of the digital chip design flow from RTL to signoff.
• Experience integrating or automating EDA tools in workflows.
• Ability to own ambiguous problems and deliver to production.

Responsibilities

• Develop and scale the RTL-to-GDSII flow infrastructure.
• Collaborate with experts to productize cutting-edge algorithms in production.
• Build infrastructure to run multi-stage design flows across EDA tools.
• Analyze design metrics to improve PPA and flow convergence.
• Deploy AI-driven methods to automate design analysis and iteration.

Skills

Python

C++

Java

AI tooling

Education

Bachelor’s degree in Computer Science, Electrical Engineering, or related technical field

Tools

EDA tools

RTL-to-GDS flow tooling

Job description

Ricrecursive Intelligence in the Palo Alto area is hiring a Software Engineer to build and scale the end-to-end RTL-to-GDSII flow. You will work across the design stack, running complex chip designs at scale and improving how we evaluate and iterate on designs within production constraints.

You will automate design analysis, integrate EDA tools, and collaborate with in‑house experts to deliver faster feedback, tighter PPA, and robust engineering workflows that support cutting‑edge AI hardware