AI Chip PnR Engineer: Placement & Routing

SambaNova, Inc.; San Jose (CA); On-site; USD 150,000 - 260,000; Full time

Benefits offered by this job

Equity

Health insurance

HSA

Wellness benefits

Job summary

SambaNova Systems in San Jose, CA, seeks engineers to develop and tune partitioning, placement, and routing for its Reconfigurable Dataflow Unit (RDU). You’ll collaborate with compiler teams, hardware architects, and performance engineers to map workloads and improve throughputs in production releases.

You will model hardware constraints, analyze performance gaps, and drive optimizations for large-scale AI workloads, including multi-turn agents and model inference.

Qualifications

• MS or PhD in CS/CE or related field.
• 3+ years of experience developing optimization or graph algorithms.
• Expert knowledge of graph algorithms, partitioning, combinatorial optimization, or MILP solvers.
• Strong proficiency in C/C++ and familiarity with Python.
• Experience designing large, parallel, performance-sensitive systems.
• Ability to learn hardware architecture and apply it to improve performance.
• Experience solving NP-hard problems in practice with heuristics or pruned methods.

Responsibilities

• Develop partitioning, placement, and routing algorithms meeting hardware constraints.
• Tune PnR results for LLM inference at varying batch sizes and concurrency.
• Model new hardware constraints in solvers and heuristics as the chip evolves.
• Analyze compiled output with performance engineers and trace throughput gaps.
• Build infrastructure for prototyping, regression testing, and deployment of PnR changes.
• Collaborate with compiler and hardware teams to define interfaces and resource models.

Skills

C/C++

Python

Graph algorithms

Optimization

Parallel systems

NP-hard heuristics

Education

MS or PhD in CS/CE or related

Tools

MILP solvers

PyTorch

MLIR

LLVM

TVM

Job description

SambaNova Systems in San Jose, CA, seeks engineers to develop and tune partitioning, placement, and routing for its Reconfigurable Dataflow Unit (RDU). You’ll collaborate with compiler teams, hardware architects, and performance engineers to map workloads and improve throughputs in production releases.

You will model hardware constraints, analyze performance gaps, and drive optimizations for large-scale AI workloads, including multi-turn agents and model inference.