AI Chip Design Architect — Document & Code Understanding

TenX Semi; San Francisco (CA); Hybrid; USD 120,000 - 170,000; Full time

Job summary

TenX Semi in San Francisco Bay Area, CA is seeking an AI Application Engineer to transform unstructured inputs into structured representations used for chip design generation.

You will build parsers for PDFs and Word docs, analyze Verilog/SystemVerilog/C code, and create multi-modal understanding including diagrams and timing charts. You will implement Retrieval Augmented Generation pipelines and translate customer change requests into structured specs, collaborating closely with chip designers.

Qualifications

• Experience with large language models and AI agents.
• Expert-level Python and production ML systems.
• Experience extracting structured information from PDFs, Word docs, or other unstructured formats.
• Experience building retrieval augmented generation pipelines.
• Familiarity with AST parsing, static analysis, or compiler techniques.

Responsibilities

• Build parsers and extractors for PDFs, Word documents, wikis, and other unstructured formats—understand technical content, not just text.
• Develop pipelines to analyze Verilog, SystemVerilog, and C code to extract architectural intent, interfaces, and constraints.
• Create multi-modal understanding for diagrams, waveforms, timing charts, and tables—the visual language of chip design.
• Build retrieval augmented generation systems to provide context from large document corpora.
• Parse customer change requests into structured delta specifications for derivative design generation.
• Collaborate with chip designers to ensure captured architectural intent and constraints are accurate.

Skills

LLM Expertise

Python Proficiency

Document Parsing

RAG Systems

Code Analysis

Problem-Solving Mindset

Tools

AST Parsing

Static Analysis

Compiler Techniques

Embeddings

Vector Databases

Retrieval Systems

Job description

TenX Semi in San Francisco Bay Area, CA is seeking an AI Application Engineer to transform unstructured inputs into structured representations used for chip design generation.

You will build parsers for PDFs and Word docs, analyze Verilog/SystemVerilog/C code, and create multi-modal understanding including diagrams and timing charts. You will implement Retrieval Augmented Generation pipelines and translate customer change requests into structured specs, collaborating closely with chip designers.