Memory Architect: PIM & AI Inference Trailblazer

Normal Computing Corporation; Mountain View (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Normal Computing is building AI inference hardware and seeks a seasoned Memory Architect to translate radical memory concepts into silicon. You will design memory floorplans, read/write paths, and novel primitives to enable high-performance compute in memory.

You will own the interface with manufacturers, drive tapeout schedules, and collaborate with analog, design, and ML teams to realize 100–1000× AI inference speedups while meeting power and reliability targets.

Qualifications

• Substantial experience in memory architecture or circuit design in memory-centric environment.
• Deep understanding of memory arrays, timing, retention and reliability.
• Hands-on memory/test-chip tapeout experience with PDKs and design rules.
• Fluency in modeling with Python/C/C++ and translating circuit behavior to architecture.

Responsibilities

• Define processing-in-memory architecture and memory floorplan for in-memory compute.
• Architect data paths and on-die fabrics to move data between memory and logic.
• Own power, thermal, ECC, and reliability to maximize performance.
• Lead tapeout planning from shuttle to test-chip content and production silicon.
• Define memory interfaces to hosts (PCIe/DDR5/LPDDR/HBM) and timing implications.

Skills

Memory architecture

RTL and SystemVerilog

Programming: Python, C, C++

Spice-level circuit modeling

Performance and power modeling

Memory interface design

Education

Bachelor's degree in Electrical Engineering

Tools

SPICE

SystemVerilog

PDK experience

Job description

Normal Computing is building AI inference hardware and seeks a seasoned Memory Architect to translate radical memory concepts into silicon. You will design memory floorplans, read/write paths, and novel primitives to enable high-performance compute in memory.

You will own the interface with manufacturers, drive tapeout schedules, and collaborate with analog, design, and ML teams to realize 100–1000× AI inference speedups while meeting power and reliability targets.