AI Accelerator Design Verification Engineer (Remote)

Acceler8 Talent

Mountain View (CA)

Remote

USD 120,000 - 210,000

Full time

3 days ago
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Job summary

Acceler8 Talent seeks a Design Verification Engineer for AI accelerator silicon, with Mountain View or remote work options. You will translate architectural intent into verification strategies, build environments and tests, and drive coverage closure across compute, memory and connectivity subsystems.

You will develop reusable SystemVerilog/UVM environments, assertion-based checks, and use simulation/formal methods to expose corner cases.

Qualifications

  • Proficient in SystemVerilog/UVM environments.
  • Experience with assertion-based verification and formal methods.
  • Strong debugging and diagnostic skills across silicon blocks and testbenches.

Responsibilities

  • Translate architectural specs into verification plans, testbenches and tests.
  • Develop reusable SystemVerilog and UVM environments and checks.
  • Use simulation and formal verification to analyze functional behavior and corner cases.
  • Drive coverage closure, diagnose failures and contribute to sign-off decisions.
  • Build portable tests/drivers for validation and post-silicon debugging.
  • Collaborate with architecture, RTL and validation teams to resolve issues.
  • Identify coverage goals and prioritize scenarios based on risks.
  • Develop protocol checks and assertions and select methods appropriately.
  • Investigate failures across testbench, model and RTL boundaries.
  • Contribute to verification reviews with clear risk reporting.

Skills

SystemVerilog
UVM
Formal verification
Simulation
Debugging
Coverage analysis
Programming for tests

Tools

Emulation
Prototyping

Job description

Acceler8 Talent seeks a Design Verification Engineer for AI accelerator silicon, with Mountain View or remote work options. You will translate architectural intent into verification strategies, build environments and tests, and drive coverage closure across compute, memory and connectivity subsystems.

You will develop reusable SystemVerilog/UVM environments, assertion-based checks, and use simulation/formal methods to expose corner cases.

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