Hands-on Digital ASIC Verification Engineer

Acceler8 Talent; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Acceler8 Talent seeks a hands-on Design Verification Engineer for a stealth AI chip startup in San Francisco. You will own verification of substantial digital ASIC blocks, build verification plans, run tests, and reproduce failures to identify root causes.

The role emphasizes autonomy, debugging, and direct collaboration with designers to ensure robust hardware. Ideal candidates have experience reading RTL and waveforms, familiarity with SystemVerilog/UVM, and a track record delivering

Qualifications

• Hands-on ownership of digital ASIC/SoC verification and clear examples of implementation.
• Ability to explain a difficult bug from exposure through reproduction and resolution.
• Strong understanding of digital logic and microarchitectural interaction with verification.

Responsibilities

• Own verification of substantial digital ASIC blocks or subsystems, from understanding the design intent to validating fixes.
• Develop verification plans, environments and tests that exercise normal operation and challenging corner cases.
• Reproduce failures and trace bugs through the test environment and RTL to isolate the underlying cause.
• Partner with design engineers on corrective changes and demonstrate that issues are resolved.
• Improve verification effectiveness through clear technical reasoning and reusable infrastructure.
• Review block and subsystem specifications with designers and identify verification risks before late-stage debug.
• Build checks and stimulus that expose interactions between control logic, state transitions and data flow.
• Reduce complex failures to reproducible cases and confirm fixes address the original issue.

Skills

Digital ASIC verification

SoC verification

Waveforms analysis

RTL reading

Debugging

Tools

SystemVerilog

UVM

Assertions

Job description

Acceler8 Talent seeks a hands-on Design Verification Engineer for a stealth AI chip startup in San Francisco. You will own verification of substantial digital ASIC blocks, build verification plans, run tests, and reproduce failures to identify root causes.

The role emphasizes autonomy, debugging, and direct collaboration with designers to ensure robust hardware. Ideal candidates have experience reading RTL and waveforms, familiarity with SystemVerilog/UVM, and a track record delivering