ML Silicon Performance Architect

OpenAI, Inc.; San Francisco (CA); On-site; USD 300,000 - 420,000; Full time

Job summary

OpenAI, Inc. is seeking an ML Silicon Performance Lead to drive hardware/software co-design for our silicon architecture.

You will work across models, kernels, compilers, and silicon to map ML workloads to hardware—and guide how the hardware should evolve to support them. You’ll partner with ML research, compiler, and silicon teams to evaluate tradeoffs, optimize kernels, data movement, quantization, and specialized IP.

Qualifications

• Experience with ML accelerator architecture and how compute resources, memory systems, and data movement shape workload performance.
• Ability to translate model and workload needs into kernel requirements and hardware design decisions.
• Experience with accelerator performance models and simulators and interpreting their results.

Responsibilities

• Drive hardware/software co-design across ML research, compiler, and silicon teams to shape kernel implementations and hardware capabilities.
• Translate model and workload needs into kernel performance targets and compute/memory requirements.
• Map and optimize ML kernels for architecture using data movement and memory hierarchy insights.
• Contribute to co-design of data structures and quantization formats across kernels, compilers, and silicon.
• Define and help develop specialized accelerator IP in collaboration with compiler and silicon partners.
• Lead performance modeling and simulation to compare designs and quantify end-to-end benefits.

Skills

ML accelerator architecture

Kernel performance targets

Data movement optimization

Hardware/software co-design

Tools

Performance models

Simulation tools

Job description

OpenAI, Inc. is seeking an ML Silicon Performance Lead to drive hardware/software co-design for our silicon architecture.

You will work across models, kernels, compilers, and silicon to map ML workloads to hardware—and guide how the hardware should evolve to support them. You’ll partner with ML research, compiler, and silicon teams to evaluate tradeoffs, optimize kernels, data movement, quantization, and specialized IP.