2nm GPIO & High-Speed Interface Engineer

Rapidus Corporation US; City of Albany (NY); Sur place; USD 130 000 - 285 000; Plein temps

Avantages offerts par ce poste

Health, Dental & Vision coverage

Résumé du poste

Rapidus Corporation is seeking talented GPIO/Interface I/O Design Engineers to develop advanced I/O solutions for 2 nm and future technologies. You will design and optimize GPIO circuits, including buffers, drivers, and level shifters, and collaborate across process, device, reliability, PDK, EDA, and IP teams.

The role emphasizes transistor-level design, HSPICE simulations, and creating robust I/O blocks for multiple voltage domains and interfaces, with a focus on high-performance, reliable

Qualifications

• B.S. or M.S. in Electrical Engineering or related field.
• 3+ years in GPIO/I/O or interface circuit design.
• CMOS design with PVT variation and reliability.
• Experience with Cadence Virtuoso, HSPICE, and LVS/DRC.

Responsabilités

• Design and optimize GPIO and interface I/O circuits for 2 nm and beyond.
• Develop I/O building blocks: buffers, drivers, receivers, level shifters, pre-drivers, termination.
• Perform transistor-level design and HSPICE simulations across PVT.
• Support SI/PI analysis and package/interface co-optimization.
• Collaborate with layout, process, reliability, DTCO, and IP teams.
• Contribute to test-chip planning, silicon characterization, and design-to-silicon correlation.

Connaissances

GPIO I/O Design

I/O Circuit Design

Signal Integrity

DTCO Knowledge

Collaboration Across Teams

Formation

B.S./M.S. in Electrical Engineering

Outils

Cadence Virtuoso

HSPICE

Siemens Calibre

Description du poste

Rapidus Corporation is seeking talented GPIO/Interface I/O Design Engineers to develop advanced I/O solutions for 2 nm and future technologies. You will design and optimize GPIO circuits, including buffers, drivers, and level shifters, and collaborate across process, device, reliability, PDK, EDA, and IP teams.

The role emphasizes transistor-level design, HSPICE simulations, and creating robust I/O blocks for multiple voltage domains and interfaces, with a focus on high-performance, reliable