Analog Designer

Staffing Technologies; Austin (TX); On-site; USD 80,000 - 110,000; Full time

Job summary

Staffing Technologies is seeking an experienced Analog Designer in Austin, Texas. The role involves supporting the integration of GPIO solutions into advanced SoC products, requiring collaboration with physical design, power integrity, and SoC engineering teams.

The ideal candidate should possess a strong background in circuit design and electrical analysis. Key responsibilities include conducting design reviews, supporting electrical analysis activities, and investigating performance issues.

A Bachelor's or Master's degree in Electrical Engineering or a related field is required.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience in analog and digital circuit design.
• Solid understanding of GPIO architecture and integration methodologies.

Responsibilities

• Provide technical guidance and conduct design reviews for digital and analog GPIO implementations.
• Support integration of GPIO IP into SoC platforms and ensure compliance.
• Perform electrical analysis related to power integrity and signal integrity.

Skills

Analog and digital circuit design

General Purpose I/O (GPIO)

Electrical analysis

Problem-solving

Communication skills

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

SPICE simulation

Job description

Our client is seeking an experienced Analog Designer with strong expertise in General Purpose I/O (GPIO), analog and digital circuit design, ESD protection, and electrical analysis to support the integration of third-party IP into advanced SoC products.

The ideal candidate will play a critical role in ensuring the successful integration, verification, and electrical performance of GPIO solutions across multiple chip designs. This position requires close collaboration with physical design, power integrity, signal integrity, and SoC engineering teams to ensure robust and reliable implementation of GPIO IP.

The successful candidate will possess a strong background in circuit design, electrical analysis, signal integrity, power integrity, and ESD methodologies, along with excellent problem-solving and communication skills.

Key Responsibilities:

• Provide technical guidance and conduct design reviews for a wide range of digital and analog GPIO implementations based on third-party licensed IP.
• Support the integration of GPIO IP into various SoC platforms and ensure compliance with design and electrical requirements.
• Perform and support electrical analysis activities related to power integrity and signal integrity to ensure reliable GPIO operation across multiple product environments.
• Collaborate with chip-level physical design teams, power integrity engineers, signal integrity engineers, and other cross‑functional stakeholders.
• Review and approve physical verification results and sign‑off checks related to GPIO implementations.
• Investigate and resolve electrical performance issues associated with GPIO interfaces.
• Develop and implement AI‑assisted methodologies and automation strategies to improve GPIO integration efficiency and engineering productivity.
• Support design validation and ensure adherence to quality, reliability, and performance requirements.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience in analog and digital circuit design.
• Solid understanding of GPIO architecture and integration methodologies.
• Experience with ESD design concepts, protection strategies, and analysis.
• Proficiency with SPICE simulation and circuit analysis tools.
• Strong understanding of power integrity concepts, including noise generation and sensitivity analysis.
• Knowledge of signal integrity fundamentals, including:
• Characteristic impedance
• Signal quality analysis
• Strong analytical, troubleshooting, and problem‑solving skills.
• Excellent communication and collaboration abilities.

Preferred Qualifications:

• Experience working with SoC, ASIC, CPU, GPU, FPGA, or semiconductor product development.
• Knowledge of clock distribution networks and clock‑related specifications, including:
• Duty Cycle Distortion (DCD)
• Clock performance analysis
• Experience leveraging AI tools and methodologies within engineering workflows.
• Experience collaborating with physical design, verification, and silicon validation teams.