Senior Layout Engineer

European Tech Recruit; Fatih; On-site; TRY 2,867,000 - 4,300,000; Full time

Job summary

European Tech Recruit is seeking a Senior Layout Engineer to own physical layout design and tape-out for advanced analog and mixed-signal IPs. You will collaborate with IC design engineers to maximize silicon performance and ensure layouts meet specifications across multiple process nodes.

Proficiency with Cadence Virtuoso, Calibre, and PVS on Linux, and 3+ years of hands-on experience in analog IC layout are required.

Qualifications

• 3+ years of hands-on analog IC layout experience with full-tape-out ownership.

Responsibilities

• Lead full-cycle IP layout execution from floorplan to tape-out.
• Optimize high-speed signals for parasitics, matching, and signal integrity.
• Apply robust floorplanning to reduce parasitics and noise across analog blocks.
• Perform physical verification (DRC, LVS, antenna) in Linux using industry tools.
• Collaborate with circuit designers and foundry teams to meet timelines.

Skills

Analog IC layout

Tape-out ownership

Analytical troubleshooting

English language

Education

Bachelor's degree in Electrical/Electronic Engineering

Tools

Cadence Virtuoso

Siemens Calibre

Cadence PVS

Job description

Our client is a growing semiconductor company driving innovation in high-performance integrated circuits. They are seeking an experienced Senior Layout Engineer to take ownership of physical layout design and tape-out execution for advanced analog and mixed-signal IPs. Working closely with IC design engineers, you will ensure that physical implementations strictly align with circuit requirements to maximize silicon performance and yield.

What You'll Do:

• Full-Cycle IP Layout Execution: Lead and execute physical layout design for a wide range of analog modules (including Bandgap, ADC/DAC, LNA, PLL, DC-DC converters, and LDOs) from initial floorplan to final tape-out.
• High-Speed & RF Optimization: Design layouts for high-performance, high-speed signals, actively collaborating with circuit designers to meet tight constraints on parasitics, matching, and signal integrity.
• Floorplanning & Noise Suppression: Apply robust layout floorplanning techniques, optimizing for parasitic reduction, latch-up prevention, and noise isolation across sensitive analog blocks.
• Physical Verification: Perform complete layout verification using industry-standard tools (Virtuoso, Calibre, PVS) within a Linux environment, driving DRC, LVS, and antenna sign-off.
• Cross-Functional Collaboration: Serve as a key link between circuit design and foundry requirements, troubleshooting issues early in the design cycle to maintain project timelines.
• Education: Bachelor's degree or higher in Electrical/Electronic Engineering or a related technical discipline.
• Experience: 3+ years of hands-on experience in analog IC layout design, with a track record of successful full project tape-outs. Top-level layout ownership across multiple foundry process nodes is strongly preferred.
• Tool Proficiency: Solid operational command of Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS in a Linux desktop environment.
• Deep Domain Knowledge: Strong understanding of semiconductor device physics, analog matching rules, latch-up mechanisms, ESD, I/O considerations, and packaging constraints.
• Languages & Soft Skills: Good written English (fluent spoken English is highly desirable), paired with strong analytical troubleshooting skills and a proactive project ownership mindset.
• Experience with ultra-high-speed chip layouts, RF processes, or BCD (Bipolar-CMOS-DMOS) technology nodes.
• Familiarity with advanced-node parasitic extraction (PEX) and post-layout simulation loops.