Senior Analog IC Layout Engineer for Tape-Out

European Tech Recruit; Fatih; On-site; TRY 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking an experienced layout professional to own the complete physical layout flow for analog and mixed-signal IP, from floorplanning through tape-out, in a Linux IC design environment.

The role requires hands-on experience with Cadence Virtuoso, Calibre, and PVS, and a strong grasp of parasitics, matching, and noise isolation, with a track record of successful tape-outs. Collaboration with circuit designers is essential to meet performance targets.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Electronic Engineering, or a related technical discipline.
• At least three years of hands-on analog IC layout design experience.
• Experience delivering complete semiconductor projects resulting in tape-out.
• Experience using Cadence Virtuoso, Siemens Calibre and/or Cadence PVS.
• Experience performing DRC, LVS, and antenna verification.
• Strong understanding of semiconductor devices, analog matching techniques, parasitics, latch-up prevention and noise isolation.
• Knowledge of ESD protection, I/O requirements and packaging constraints.
• Strong analytical and troubleshooting abilities.
• Proactive ownership and cross-functional collaboration.
• Ownership of top-level layout across multiple foundry process nodes.
• Experience with ultra-high-speed or RF IC layouts.
• Knowledge of BCD process technologies.
• Familiarity with advanced-node parasitic extraction and post-layout simulation loops.

Responsibilities

• Own the complete physical layout flow for analog and mixed-signal IP, from initial floorplanning to tape-out delivery.
• Develop layouts for blocks such as bandgap references, ADCs, DACs, LNAs, PLLs, DC-DC converters, and LDOs.
• Implement layouts for high-speed and RF circuits while meeting parasitic, matching and signal-integrity requirements.
• Work closely with circuit designers to ensure the physical implementation accurately reflects electrical and performance requirements.
• Create effective floorplans that minimise parasitics, prevent latch-up, and isolate noise-sensitive circuitry.
• Apply appropriate matching, shielding, guard-ring, routing, and device-placement techniques.
• Complete DRC, LVS, and antenna verification using Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS.
• Work confidently within a Linux-based IC design environment.
• Identify and resolve physical verification and manufacturability issues before final sign-off.
• Coordinate between circuit design requirements and foundry design rules to protect project schedules.
• Support parasitic extraction and post-layout simulation activities.
• Prepare final layout databases for successful tape-out.

Skills

Analog IC layout

Layout design

Ownership & ownership mindset

Cross-functional collaboration

Problem solving

Education

Bachelor’s degree in Electrical Engineering or related

Tools

Cadence Virtuoso

Siemens Calibre

Cadence PVS

Job description

European Tech Recruit is seeking an experienced layout professional to own the complete physical layout flow for analog and mixed-signal IP, from floorplanning through tape-out, in a Linux IC design environment.

The role requires hands-on experience with Cadence Virtuoso, Calibre, and PVS, and a strong grasp of parasitics, matching, and noise isolation, with a track record of successful tape-outs. Collaboration with circuit designers is essential to meet performance targets.