(Analog) Layout Engineer

European Tech Recruit; Fatih; On-site; TRY 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking an experienced layout professional to own the complete physical layout flow for analog and mixed-signal IP, from floorplanning through tape-out, in a Linux IC design environment.

The role requires hands-on experience with Cadence Virtuoso, Calibre, and PVS, and a strong grasp of parasitics, matching, and noise isolation, with a track record of successful tape-outs. Collaboration with circuit designers is essential to meet performance targets.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Electronic Engineering, or a related technical discipline.
• At least three years of hands-on analog IC layout design experience.
• Experience delivering complete semiconductor projects resulting in tape-out.
• Experience using Cadence Virtuoso, Siemens Calibre and/or Cadence PVS.
• Experience performing DRC, LVS, and antenna verification.
• Strong understanding of semiconductor devices, analog matching techniques, parasitics, latch-up prevention and noise isolation.
• Knowledge of ESD protection, I/O requirements and packaging constraints.
• Strong analytical and troubleshooting abilities.
• Proactive ownership and cross-functional collaboration.
• Ownership of top-level layout across multiple foundry process nodes.
• Experience with ultra-high-speed or RF IC layouts.
• Knowledge of BCD process technologies.
• Familiarity with advanced-node parasitic extraction and post-layout simulation loops.

Responsibilities

• Own the complete physical layout flow for analog and mixed-signal IP, from initial floorplanning to tape-out delivery.
• Develop layouts for blocks such as bandgap references, ADCs, DACs, LNAs, PLLs, DC-DC converters, and LDOs.
• Implement layouts for high-speed and RF circuits while meeting parasitic, matching and signal-integrity requirements.
• Work closely with circuit designers to ensure the physical implementation accurately reflects electrical and performance requirements.
• Create effective floorplans that minimise parasitics, prevent latch-up, and isolate noise-sensitive circuitry.
• Apply appropriate matching, shielding, guard-ring, routing, and device-placement techniques.
• Complete DRC, LVS, and antenna verification using Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS.
• Work confidently within a Linux-based IC design environment.
• Identify and resolve physical verification and manufacturability issues before final sign-off.
• Coordinate between circuit design requirements and foundry design rules to protect project schedules.
• Support parasitic extraction and post-layout simulation activities.
• Prepare final layout databases for successful tape-out.

Skills

Analog IC layout

Layout design

Ownership & ownership mindset

Cross-functional collaboration

Problem solving

Education

Bachelor’s degree in Electrical Engineering or related

Tools

Cadence Virtuoso

Siemens Calibre

Cadence PVS

Job description

Our client is a growing semiconductor business developing high-performance integrated circuits. The company is expanding its engineering team and is looking for an experienced layout professional to support the delivery of advanced analog and mixed-signal IP.

The Opportunity

This is a hands-on role with responsibility for the complete physical layout process, from early floorplanning and detailed implementation through physical verification and tape-out.

Working closely with analog and mixed-signal IC designers, you will translate circuit requirements into robust physical implementations. Your layouts will need to meet demanding targets for performance, matching, parasitics, signal integrity, reliability, and manufacturing yield.

The position would suit an engineer who can work independently, resolve complex layout challenges, and take genuine ownership of projects through to tape-out.

Key Responsibilities

• Own the complete physical layout flow for analog and mixed-signal IP, from initial floorplanning to tape-out delivery.
• Develop layouts for blocks such as bandgap references, ADCs, DACs, LNAs, PLLs, DC-DC converters, and LDOs.
• Implement layouts for high-speed and RF circuits while meeting demanding parasitic, matching, and signal-integrity requirements.
• Work closely with circuit designers to ensure the physical implementation accurately reflects electrical and performance requirements.
• Create effective floorplans that minimise parasitics, prevent latch-up, and isolate noise-sensitive circuitry.
• Apply appropriate matching, shielding, guard-ring, routing, and device-placement techniques.
• Complete DRC, LVS, and antenna verification using Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS.
• Work confidently within a Linux-based IC design environment.
• Identify and resolve physical verification and manufacturability issues before final sign-off.
• Coordinate between circuit design requirements and foundry design rules to protect project schedules.
• Support parasitic extraction and post-layout simulation activities.
• Prepare final layout databases for successful tape-out.

Required Experience

• A bachelor’s degree or higher in Electrical Engineering, Electronic Engineering, or a related technical discipline.
• At least three years of hands-on experience in analog IC layout design.
• Previous involvement in complete semiconductor projects resulting in successful tape-outs.
• Practical experience using Cadence Virtuoso, Siemens Calibre, and/or Cadence PVS.
• Experience performing DRC, LVS, and antenna verification.
• A strong understanding of semiconductor devices, analog matching techniques, parasitic effects, latch-up prevention, and noise isolation.
• Knowledge of ESD protection, I/O requirements, and packaging constraints.
• Strong analytical and troubleshooting abilities.
• A proactive approach to project ownership and cross-functional collaboration.
• Ownership of top-level layout across multiple foundry process nodes.
• Experience with ultra-high-speed or RF IC layouts.
• Knowledge of BCD process technologies.
• Familiarity with advanced-node parasitic extraction and post-layout simulation loops.

Why Consider This Opportunity?

You will have the opportunity to own complex layout projects from floorplan through to tape-out while working closely with experienced IC designers. The position offers exposure to a broad range of advanced analog and mixed-signal circuits and the chance to influence silicon performance, reliability, and yield directly.