SoC Digital Design Engineer, Multimedia Lab Singapore Regular

ByteDance; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

ByteDance is seeking a skilled digital front-end designer in Singapore. The role involves architecture design, RTL implementation, and collaboration with cross-functional teams for SoC development. Candidates must have a Bachelor's degree in relevant fields and demonstrated experience in digital circuit design.

The ideal applicant will be proficient in Verilog/SystemVerilog, EDA tools, and scripting languages, with a focus on producing high-quality designs and achieving power optimization.

Qualifications

• 3+ years of experience in digital front-end design.
• Fluency in at least one scripting language for workflow automation.
• Understanding of NPU architecture and AI hardware acceleration is a plus.

Responsibilities

• Participate in defining the architecture of SoC top or subsystems.
• Write high-quality, well-structured RTL code and maintain design documentation.
• Perform quality control checks to ensure design robustness.
• Collaborate with teams for debugging and optimization.
• Engage in low-power design techniques and strategies.

Skills

Verilog/SystemVerilog

EDA Tools (Spyglass, Design Compiler, PrimeTime)

Scripting (Python, Perl, Tcl, Makefile)

Digital Circuit Design

Education

Bachelor's degree in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering

Job description

Responsibilities

1. Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
2. RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
3. Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
4. Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
5. Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.

Qualifications

Minimum Qualifications

• Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
• 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
• Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
• Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.

Preferred Qualifications

• Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
• Proven experience in SoC-level performance profiling and bottleneck analysis.
• Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
• Successful tape-out experience in advanced process nodes (7nm/5nm/3nm).