Staff Layout Engineer

Broadcom Singapore Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom Singapore Pte Ltd is seeking a Staff Layout Engineer for its Library Group within the Central Engineering Group. The role focuses on IC layout for memory, I/O, and standard cells, with emphasis on advanced submicron processes.

You will apply layout guidelines, perform floor-planning, and ensure timely, quality layout and verification. Analog experience is a plus and relocation to Singapore is required.

Qualifications

• 8+ years of IC layout experience in submicron CMOS processes.
• Strong memory, I/O, and standard cell layout experience.
• Proficiency with Cadence tools and CALIBRE/Hercules.
• Experience in digital layout; analog layout is a plus.

Responsibilities

• IC Layout.
• Understand and apply layout guidelines (standard cells, I/O memories), new process rules and other technical requirements; schedule layout floor-planning.
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer).
• Adapt quickly to new methodologies; communicate well with the library team.

Skills

IC Layout

Memory layout

Cadence layout

Cadence schematic capture

CALIBRE verification

Hercules verification

Floor-planning

Hierarchy layout

Memory compiler

SKILL scripting

Lead or train a team

Tools

Cadence Virtuoso

CALIBRE

Hercules verification tools

Job description

Staff Layout Engineer

Job descriptions and the level of expertise:

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements

• IC Layout
• Strong layout knowledge with a minimum of 8 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm,2nm ,A14 and below
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job description

• IC Layout
• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
  Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem)

• Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Experience in memory compiler will be a plus.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge of memory layout topology.
• Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with the ability to work independently as well as in a team.
• Good leadership quality in project management.

Re-location

• Must be available to re-locate to Singapore immediately.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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