Staff DDR5/LPDDR5 Memory Verification Engineer

Advanced Micro Devices; Singapore; Hybrid; SGD 90,000 - 140,000; Full time

Job summary

Advanced Micro Devices, based in Singapore, is seeking an experienced Verification Engineer to drive memory interface verification for DDR5/LPDDR5 in server products. The role requires SystemVerilog, UVM, C/C++, and scripting skills, with exposure to HW/SW/FW integration across multiple teams.

You will mentor peers, optimize verification methodologies, and support post-Si validation to resolve performance and power issues.

Qualifications

• Experience with SystemVerilog/UVM-based testbenches, simulation environments and coverage models for DDR5/LPDDR5 systems.
• Ability to collaborate across hardware, firmware and software teams early in the design cycle to align memory architecture and validation requirements.
• Proven track record building memory interface verification components (VIPs/BFMs) from scratch.

Responsibilities

• Develop and execute verification plans for DDR5, LPDDR5 and DFI memory systems in server products.
• Ensure complete system interactions with HW, FW, BIOS and SW are aligned to enable features of memory interfaces.
• Engage in cross-functional discussions with IP/Domain Architects and Design engineers for planning and debugging.
• Share verification methodology knowledge and contribute to improving processes.
• Support Post-Si teams for product performance, power and functional issue resolution.

Skills

SystemVerilog

UVM

C/C++

Python

DDR5 memory

LPDDR5/LPDDR6

Memory systems

Collaboration

Communication

Education

Bachelor’s or Master’s degree

Tools

VIPs

BFMs

GLS

NLP

XPROP

Job description

Advanced Micro Devices, based in Singapore, is seeking an experienced Verification Engineer to drive memory interface verification for DDR5/LPDDR5 in server products. The role requires SystemVerilog, UVM, C/C++, and scripting skills, with exposure to HW/SW/FW integration across multiple teams.

You will mentor peers, optimize verification methodologies, and support post-Si validation to resolve performance and power issues.