SerDes Verification Engineer for High‑Speed Links & Protocols

Advanced Micro Devices; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices in Singapore seeks a SerDes Verification Engineer to verify high‑speed SerDes interfaces, run timing and protocol checks, and validate signal integrity metrics. You will collaborate with hardware and design teams to ensure adherence to UCIe, PCIe, Ethernet, DDR and other protocols, developing testbenches and automated tests to support robust silicon validation.

The role demands strong analytical skills, hands‑on verification experience with UVM/SystemVerilog, and effective

Qualifications

• Experience in verifying SerDes interfaces and high-speed signaling.
• Strong knowledge of verification methodologies (e.g., UVM, SystemVerilog).
• Ability to collaborate across multiple sites/timezones and communicate effectively.

Responsibilities

• Verification of SerDes designs and IPs, developing testbenches and verification plans.
• Drive formal verification for blocks and write properties/assertions.
• Simulate, debug timing/protocol issues, and evaluate jitter/BER/eye diagrams.
• Collaborate with design/hardware teams to ensure protocol compliance (UCIe, PCIe, DDR).
• Develop automated regression tests to ensure robustness across versions.

Skills

SerDes verification

High-speed signaling

Debugging

Team collaboration

Analytical thinking

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

UVM

SystemVerilog

VHDL

Job description

Advanced Micro Devices in Singapore seeks a SerDes Verification Engineer to verify high‑speed SerDes interfaces, run timing and protocol checks, and validate signal integrity metrics. You will collaborate with hardware and design teams to ensure adherence to UCIe, PCIe, Ethernet, DDR and other protocols, developing testbenches and automated tests to support robust silicon validation.

The role demands strong analytical skills, hands‑on verification experience with UVM/SystemVerilog, and effective