Synthesis & STA Engineer -Singapore

PICOHEART (SG) PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

ByteDance seeks an experienced IC Design Engineer to drive the silicon design flow from RTL to GDSII, focusing on synthesis, SDC constraints, and power optimization for advanced chip projects. The role collaborates with frontend and backend teams to ensure tight timing and robust DFT integration.

The candidate brings 3+ years in IC design, strong Verilog/SystemVerilog and EDA tool proficiency, and a track record in low‑power implementation and timing closure.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
• 3+ years of experience in IC design with a focus on sdc, synthesis, timing signoff, low‑power implementation, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to‑GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP).

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constrains (SDC) preparation and tuning, and conduct hierarchical/full‑chip STA signoff and timing closure.
• Implement low‑power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front‑end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Verilog/SystemVerilog

Synthesis

Timing signoff

Low-power design

Power optimization

SDC

RTL-to-GDSII flow

EDA tools

Fusion Compiler

Genus/Innovus

PrimeTime/Tempus

Formality

Conformal LP

Education

Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field

Tools

Fusion Compiler

Genus/Innovus

PrimeTime/Tempus

Formality

Conformal LP

Job description

About Us

Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.

Why Join ByteDance

Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.

As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.

Diversity & Inclusion

ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.

Responsibilities

Team Introduction

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape‑out, mass production, packaging, testing, and board‑level verification. They collaborate closely with front‑end chip teams across business units to drive R&D progress and mass production deployment for chip.

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constrains (SDC) preparation and tuning, and conduct hierarchical/full‑chip STA signoff and timing closure.
• Implement low‑power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front‑end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Minimum Qualifications

• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
• 3+ years of experience in IC design with a focus on sdc, synthesis, timing signoff, low‑power implementation, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to‑GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP).

Preferred Qualifications

• Strong understanding of timing analysis, multi‑clock domain handling.
• Familiarity with DFT methodologies (scan, bscan, mbist) and understanding of DFT related timing analysis is preferred.