Physical Design Engineer

Bitmain; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Bitmain seeks a senior digital physical design engineer to own RTL to GDS implementation and signoff, with emphasis on STA analysis and SPICE‑based timing checks.

You will develop and maintain PR/PV/PI/STA design flows, supporting advanced nodes and EDA tool integration to improve efficiency and reliability.

Qualifications

• Complete digital physical design flow (RTL to GDS) and related EDA tools.
• Experience in top-level PR/PI/PV/BUMP planning and signoff standards.
• Familiar with ultra-low-voltage, large-scale IP tape-out environments.
• Knowledge of low-power design methodologies and power analysis flows.
• Strong scripting skills in Tcl, Python, Perl, C or C++.

Responsibilities

• RTL to GDS full-chip physical implementation and PV/PI signoff.
• Perform full-chip STA signoff and SPICE simulation for critical timing paths.
• Develop, optimize, and maintain PR/PV/PI/STA design flows; support new nodes.

Skills

RTL to GDS

STA analysis

PPA optimization

Low-power design

Tape-out experience

Tcl

Python

C/C++

3D IC design

Signoff standards

PR/PI/PV planning

Tools

INVS

FC

PT

PX

RH

Calibre

DC

Job description

• 1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths;
• 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools;
• 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.

Requirement

• 1. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes;
• 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage;
• 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred;
• 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++;
• 5. Familiar with 3D IC design; relevant experience is a plus;
• 6. Prior experience with STA signoff in tape-out projects is preferred.