SoC Verification Engineer: NoC, UVM & VIP Expert

Infineon Technologies AG; Singapore; On-site; SGD 90,000 - 160,000; Full time

Job summary

Infineon Technologies AG in Singapore is seeking an experienced Chip Verification Engineer to execute end-to-end verification of complex SoC designs with a focus on Network-on-Chip (NoC) interconnect and system-level verification. You will develop verification plans, build SystemVerilog/UVM testbenches and VIPs, and run simulations across RTL, unit-delay and gate-level environments.

The role offers the opportunity to lead technically, guide mid/long-term goals, and collaborate with global teams

Qualifications

• Master's or Bachelor's in Electrical Engineering or Computer Science with 5–12 years of relevant work experience.
• Strong SystemVerilog and UVM knowledge with hands-on testbench development.
• Experience in NOC verification and AMBA/AHB/AXI protocol integration is a plus.
• Hardware‑software debugging across RTL to system level and familiarity with version control.
• Ability to lead technically and mentor a team for more senior roles.

Responsibilities

• Develop verification plans and write SystemVerilog/UVM test benches.
• Integrate 3rd party VIP components and verify NOC interconnects.
• Simulate and debug RTL, unit delay, and gate-level environments using the indicated toolchain.
• Collaborate with verification teams to align goals and optimize coverage.
• Lead a team in advanced environments and identify long-term improvement areas.

Skills

SystemVerilog

UVM

C/C++

NOC verification

Debugging

Education

Master's or Bachelor's in Electrical Engineering or Computer Science

Tools

Xcelium

Spectre

Simvision

GitLab

Git/Bitbucket

ClearCase

CVS

SVN

Job description

Infineon Technologies AG in Singapore is seeking an experienced Chip Verification Engineer to execute end-to-end verification of complex SoC designs with a focus on Network-on-Chip (NoC) interconnect and system-level verification. You will develop verification plans, build SystemVerilog/UVM testbenches and VIPs, and run simulations across RTL, unit-delay and gate-level environments.

The role offers the opportunity to lead technically, guide mid/long-term goals, and collaborate with global teams