Senior Chip Verification Engineer – NoC/UVM Lead

Infineon; Singapore; In loco; SGD 90.000 - 150.000; Tempo pieno

Descrizione del lavoro

Infineon Technologies seeks an experienced Chip Verification Engineer to lead end-to-end verification of complex SoC designs, focusing on Network-on-Chip interconnects. The role includes developing verification plans, building SystemVerilog/UVM testbenches and VIPs, and creating C/C++ and Perspec test cases, with validation across RTL, unit-delay and gate-level environments.

Candidates should have 5–12 years in chip verification, deep SystemVerilog/UVM expertise, and hands-on experience with

Competenze

• 5–12 years of relevant work experience in chip verification.
• Strong SystemVerilog and UVM expertise.
• Experience with NOC/AMBA/AXI verification and VIP integration.
• Hands-on with Xcelium, Spectre and Simvision for simulation/debug.
• Proficient in version control and bug-tracking tools.

Mansioni

• Execute end-to-end verification of SoC designs including NoC interconnects.
• Develop verification plans and build SystemVerilog/UVM test benches and VIPs.
• Create C/C++ and Perspec test cases and drive verification across RTL and gate-level.
• Simulate and debug using Emulators, Portable Stimulus, and formal methods as needed.
• Collaborate with team to review requirements and guide junior colleagues.

Conoscenze

SystemVerilog

UVM

NOC verification

AMBA/AXI

Xcelium

Spectre

Simvision

Git

Formazione

Masters/Bachelors in Electrical Engineering or Computer Science

Strumenti

Gitlab

Git/Bitbucket

ClearCase

CVS

SVN

Descrizione del lavoro

Infineon Technologies seeks an experienced Chip Verification Engineer to lead end-to-end verification of complex SoC designs, focusing on Network-on-Chip interconnects. The role includes developing verification plans, building SystemVerilog/UVM testbenches and VIPs, and creating C/C++ and Perspec test cases, with validation across RTL, unit-delay and gate-level environments.

Candidates should have 5–12 years in chip verification, deep SystemVerilog/UVM expertise, and hands-on experience with