Hybrid SoC Verification Engineer II (SystemVerilog/UVM)

Silicon Labs Careers; Singapore; On-site; SGD 100,000 - 150,000; Full time

Benefits offered by this job

Medical and dental insurance coverage

Bi yearly health screening

Office located near Tai Seng MRT

Job summary

Silicon Labs seeks an experienced SoC verification engineer to join our IoT Digital Design team in Singapore. You will develop and execute verification plans for Wireless MCU SoCs, build SystemVerilog/UVM testbenches, and drive coverage closure across RTL and emulation environments.

You will collaborate with RTL, architecture, firmware, and validation teams, mentoring junior engineers while advancing verification methodologies and CI flows.

Qualifications

• BS/MS in Electrical or Computer Engineering.
• 5–10+ years of verification experience.
• Experience with Wireless SoCs and MCU subsystems.
• Knowledge of AMBA/AXI/APB protocols.
• Strong SystemVerilog/UVM skills.
• Proficiency in Python/Perl/TCL scripting.

Responsibilities

• Develop and execute verification plans for SoC/IP blocks.
• Build and maintain SystemVerilog/UVM-based testbenches.
• Create directed and constrained-random test cases.
• Drive functional coverage closure and regression analysis.
• Debug RTL and verification failures across sim/emu environments.
• Collaborate with RTL, architecture, firmware, and validation teams.
• Mentor junior engineers and contribute to verification strategy.

Skills

SystemVerilog/UVM

RTL/GLS simulation

Python scripting

Functional coverage

Testbench development

Debug verification

AMBA/AXI/APB

SoC/IP verification

Low-power verification

CDC/RDC verification

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

SystemVerilog

UVM/OVM

Simulators

Job description

Silicon Labs seeks an experienced SoC verification engineer to join our IoT Digital Design team in Singapore. You will develop and execute verification plans for Wireless MCU SoCs, build SystemVerilog/UVM testbenches, and drive coverage closure across RTL and emulation environments.

You will collaborate with RTL, architecture, firmware, and validation teams, mentoring junior engineers while advancing verification methodologies and CI flows.