Senior Digital Engineer

SILICON LABORATORIES INTERNATIONAL PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Benefits offered by this job

Medical Insurance

Dental Coverage

Office near Tai Seng MRT

Job summary

SILICON LABORATORIES INTERNATIONAL PTE. LTD. is seeking a Design Engineer to drive the physical design of complex SoCs, covering synthesis, floorplanning, place-and-route and sign-off flows. You will optimise power, performance and area while ensuring robust timing closure.

Collaborate with RTL, DFT, verification and packaging teams; lead EDA tool flow improvements and mentor junior engineers. Office location is in Singapore, with opportunities to work with foundries on process readiness.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 4+ years of ASIC physical design experience.
• Hands-on experience with Synopsys and Cadence tool suites.
• Strong timing analysis, low-power methods and ECO flows.
• Knowledge of architecture-to-GDSII flows and sign-off requirements.

Responsibilities

• Drive end-to-end physical design flow for complex SoCs and IPs.
• Define floorplanning, CTS, placement, routing and timing closure strategies.
• Own power, performance and area metrics for assigned designs.
• Manage constraints, synthesis strategies and sign-off criteria.
• Collaborate with RTL, DFT, verification and packaging teams.
• Advance EDA tool flow automation and methodology improvements.
• Mentor and guide junior engineers in design excellence.
• Coordinate with foundries and vendors on process bring-up and tape-out readiness.

Skills

End-to-end physical design flow

Floorplanning

Clock-tree synthesis

Placement and routing

Timing closure

Power optimization

PPA optimization

DFT familiarity

Team mentorship

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

4+ years of ASIC physical design experience

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

Cadence Innovus

Tempus

DFT tools

Job description

What we’re looking for:

We are seeking a highly skilled Design Engineer to join our Silicon Engineering team. This role involves driving the design, implementation, and optimization of cutting-edge SoCs through advanced physical design methodologies. The ideal candidate will have deep expertise in synthesis, floorplanning, place-and-route, timing closure, power/performance optimization, and sign-off flows.

Skills you’ll need:

• Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).
• Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies.
• Own and optimize power, performance, and area (PPA) metrics for assigned designs.
• Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS).
• Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration.
• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.
• Mentor and guide junior engineers, fostering technical growth and design excellence.
• Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.

Education and/or Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
• 4+ years of experience in ASIC physical design
• Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime),
• Cadence (Innovus, Tempus), or equivalent.
• Strong background in timing analysis, low-power methodologies, and ECO flows.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Experience with chip-level integration and hierarchical design methodologies.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).
• Familiarity with DFT, STA, and physical verification methodologies.
• Exposure to multi-clock, multi-voltage, and multi-domain designs
• Excellent problem-solving and communication skills.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station