Senior Verification Engineer: RTL/UVM Specialist

BITDEER DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Bitdeer Technologies Group is seeking an experienced verification engineer to design and execute advanced verification tasks using UVM and SystemVerilog. You will work on RTL development, co-simulation, and emulation across multiple platforms in a fast-paced, collaborative team.

You will contribute to coverage-driven verification, develop test plans, and document results to support verification sign-off. A strong background in digital logic, HDL, and scripting is essential for success.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or currently pursuing).
• Solid understanding of digital logic design and RTL development using Verilog or HDL.
• Proficiency with AMBA bus protocols (AXI, AHB, APB).
• Hands-on RTL simulation, debugging, and waveform analysis with industry-standard EDA tools.

Responsibilities

• Apply UVM, SystemVerilog, Verilog, and SVA in verification tasks.
• Develop verification methodologies including UVM, C/C++, co-simulation, and mixed-mode emulation.
• Contribute to projects using Palladium Z1, HAPS, and Zebu platforms.
• Collaborate with verification and design engineers to define and refine test plans.
• Implement test cases, stimuli, and patterns to validate DUT functionality and corner cases.
• Run simulations and analyze RTL issues using waveform analysis tools.
• Maintain regression test suites and monitor coverage metrics.
• Document test results, coverage, and verification sign-off.

Skills

UVM

SystemVerilog

Verilog

C/C++

RTL design

Waveform analysis

Linux scripting

Education

Electrical Engineering

Computer Engineering

Computer Science

Tools

Palladium Z1

HAPS

Zebu

Synopsys

Cadence

Mentor

Job description

Bitdeer Technologies Group is seeking an experienced verification engineer to design and execute advanced verification tasks using UVM and SystemVerilog. You will work on RTL development, co-simulation, and emulation across multiple platforms in a fast-paced, collaborative team.

You will contribute to coverage-driven verification, develop test plans, and document results to support verification sign-off. A strong background in digital logic, HDL, and scripting is essential for success.