Senior IC Verification Lead – UVM/SystemVerilog

Bitdeer Group; Singapore; On-site; SGD 70,000 - 100,000; Full time

Benefits offered by this job

Attractive welfare benefits

Training and mentoring opportunities

Inclusive and diverse environment

Job summary

Bitdeer Group, headquartered in Singapore, is seeking a talented Design Verification Engineer to join our IC development team. In this role, you'll develop verification environments and work closely with design and verification teams to ensure robust digital designs.

Ideal candidates should have a strong background in digital logic design, familiarity with EDA tools, and excellent communication skills in English. You will enjoy a dynamic work culture that values diversity and offers fast growth opportunities in the digital asset industry.

Qualifications

• Solid understanding of RTL simulation and debugging.
• Experience with industry-standard EDA tools.
• Familiarity with Linux/Unix environments for automation.

Responsibilities

• Develop comprehensive verification environments.
• Collaborate with design teams for verification test plans.
• Execute simulations and analyze/debug RTL issues.

Skills

Digital logic design

RTL development using Verilog

Proficiency with SystemVerilog

Hands-on EDA tools experience

Strong debugging skills

Good communication skills in English

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Synopsys

Cadence

Git

Job description

Bitdeer Group, headquartered in Singapore, is seeking a talented Design Verification Engineer to join our IC development team. In this role, you'll develop verification environments and work closely with design and verification teams to ensure robust digital designs.

Ideal candidates should have a strong background in digital logic design, familiarity with EDA tools, and excellent communication skills in English. You will enjoy a dynamic work culture that values diversity and offers fast growth opportunities in the digital asset industry.