Senior Verification Engineer – SystemVerilog/UVM

BITDEER DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Benefits offered by this job

Welfare benefits

Training and mentoring

Job summary

Bitdeer Technologies Group in Singapore seeks a verification engineer to implement UVM-based verification, SystemVerilog/Verilog, and SVA across RTL designs. You will develop test plans, create stimuli, execute simulations, and debug complex RTL issues.

Join a high-impact team leveraging Palladium Z1, HAPS and Zebu platforms, with strong emphasis on coverage, regression, and sign-off readiness in a fast-growing crypto-asset environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
• Solid understanding of digital logic design and RTL development using Verilog or similar HDLs.
• Proficiency with AMBA bus protocols (AXI, AHB, APB).
• Hands-on experience with RTL simulation, debugging, and waveform analysis using EDA tools.
• Proficiency with SystemVerilog and UVM verification methodologies.
• Familiarity with Linux/Unix environments and scripting for automation.
• Experience with version control systems (Git or SVN).
• Strong analytical and debugging skills, clear verification reporting.

Responsibilities

• Apply UVM, SystemVerilog, Verilog and SVA for verification tasks.
• Develop and implement verification methodologies including UVM, C/C++, co-simulation and emulation.
• Contribute to projects using Palladium Z1, HAPS and Zebu platforms.
• Collaborate with verification and design teams to define and refine test plans.
• Create test cases, stimuli and patterns to validate DUT and corner cases.
• Execute simulations and debug RTL issues using waveform analysis.
• Maintain regression test suites and improve coverage metrics.
• Document verification results and contribute to verification sign-off.

Skills

UVM

SystemVerilog

Verilog

C/C++ programming

RTL design understanding

Linux scripting (Python)

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Palladium Z1

HAPS

Zebu platforms

Synopsys

Cadence

Siemens EDA / Mentor

Git

Job description

Bitdeer Technologies Group in Singapore seeks a verification engineer to implement UVM-based verification, SystemVerilog/Verilog, and SVA across RTL designs. You will develop test plans, create stimuli, execute simulations, and debug complex RTL issues.

Join a high-impact team leveraging Palladium Z1, HAPS and Zebu platforms, with strong emphasis on coverage, regression, and sign-off readiness in a fast-growing crypto-asset environment.