Senior SerDes Verification Engineer: High-Speed IP & Protocols

Advanced Micro Devices (S) Pte Ltd; Singapore; On-site; SGD 90,000 - 130,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD in Singapore is seeking a SerDes Verification Engineer to design and validate high-speed SerDes interfaces. You will develop testbenches using UVM and SystemVerilog, run simulations, and debug timing and protocol issues to ensure compliance with UCIe, PCIe, and DDR standards.

You will collaborate with hardware and design teams across sites, perform signal integrity analysis, and drive automated regression tests to ensure robust verification across versions.

Qualifications

• Bachelors or Masters degree in Computer Engineering or Electrical Engineering.
• Experience with high-speed SerDes verification and protocols.
• Strong analytical and problem-solving skills; good communication across sites/time zones.

Responsibilities

• Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs and subsystems to ensure functional and performance requirements.
• Drive formal verification for the block and write formal properties and assertions to verify the design.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
• Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
• Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, BER, signal integrity, eye diagrams, and other key metrics.
• Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated Testing: Develop automated regression tests to ensure robustness and stability of the SerDes design over multiple versions and iterations.
• Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
• Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
• Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies

Skills

UVM

SystemVerilog

Verilog

VHDL

Signal integrity

BER testing

Eye diagrams

Python scripting

Automation

Debugging

DDR

UCIe

PCIe

Education

Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Tools

UVM

SystemVerilog

Verilog/VHDL

Job description

AMD in Singapore is seeking a SerDes Verification Engineer to design and validate high-speed SerDes interfaces. You will develop testbenches using UVM and SystemVerilog, run simulations, and debug timing and protocol issues to ensure compliance with UCIe, PCIe, and DDR standards.

You will collaborate with hardware and design teams across sites, perform signal integrity analysis, and drive automated regression tests to ensure robust verification across versions.