Senior SerDes Verification Engineer - High-Speed IP

AMD; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD is seeking a SerDes Verification Engineer in Singapore to verify high-speed SerDes interfaces, test SI, BER, and eye diagrams. You will collaborate with design and hardware teams to ensure protocol compliance with UCIe, PCIe, DDR, and other standards.

You will develop verification plans, build testbenches in UVM/SystemVerilog, run simulations, and debug timing/protocol issues while contributing to continuous improvement of verification methodologies.

Qualifications

• Bachelor's or Master's in CSE/EE and related field.
• Strong experience with high-speed SerDes verification.
• Hands-on verification using UVM/SystemVerilog.
• Familiar with DDR/UCIe/PCIe protocols and signal integrity.

Responsibilities

• Develop and execute verification plans and testbenches for SerDes IPs.
• Drive formal verification and create coverage metrics.
• Design testbenches using UVM, SystemVerilog, and VHDL.
• Analyze timing, protocol errors, and debug failures with RTL/firmware teams.
• Automate regression tests and document verification results.

Skills

SerDes verification

UVM

SystemVerilog

Python scripting

PCIe/UCIe protocols

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

UVM

SystemVerilog

VHDL/Verilog

Python

Perl

Job description

AMD is seeking a SerDes Verification Engineer in Singapore to verify high-speed SerDes interfaces, test SI, BER, and eye diagrams. You will collaborate with design and hardware teams to ensure protocol compliance with UCIe, PCIe, DDR, and other standards.

You will develop verification plans, build testbenches in UVM/SystemVerilog, run simulations, and debug timing/protocol issues while contributing to continuous improvement of verification methodologies.