Senior Signal Integrity Engineer – 112G/224G SerDes

Silith; Singapore; Hybrid; SGD 120,000 - 180,000; Full time

Job summary

Silith in Singapore is seeking a Signal Integrity Engineer to lead high-speed SI design, simulation, and validation for CPO systems. You will optimize SerDes channels, interconnects, and interfaces from chiplet to system level, collaborating across silicon, packaging, and system teams to maximize performance and minimize loss.

You will design, simulate, and test 56G/112G/224G PAM4 links, develop SI models (IBIS, S-parameters), and correlate results with measurements to drive robust high-speed

Qualifications

• Master’s degree or higher in Electronics or a related field.
• 3+ years of experience in signal integrity for high-speed digital systems.
• Deep knowledge of 56G/112G/224G PAM4 SerDes links and high-speed signaling.
• Experience with PCB, packages, interposers, RDLs and connectors.
• Ability to correlate simulation with measurement data.

Responsibilities

• Lead SI design, simulation, analysis, and validation for high-speed paths in optical engines and optoelectronic systems.
• Design and optimize high-speed SerDes channels between ASICs, DSPs, drivers, TIAs, connectors, packages, interposers, and PCBs.
• Perform channel modeling and SI simulation for 112G, 224G PAM4, and next-gen interfaces.
• Analyze insertion loss, return loss, crosstalk, impedance, eye diagrams, jitter, and related SI parameters.
• Develop and maintain SI models (IBIS, IBIS-AMI, S-parameters) and perform channel/system-level SI analysis.
• Correlate simulation results with measurement data and optimize designs.

Skills

Signal integrity

High-speed analysis

Cross-functional collaboration

Test equipment use

Education

Master’s degree or above in Electronics or related field

Tools

Cadence Sigrity

Keysight ADS

Ansys HFSS

Ansys SIwave

Q3D

HyperLynx

Job description

Silith in Singapore is seeking a Signal Integrity Engineer to lead high-speed SI design, simulation, and validation for CPO systems. You will optimize SerDes channels, interconnects, and interfaces from chiplet to system level, collaborating across silicon, packaging, and system teams to maximize performance and minimize loss.

You will design, simulate, and test 56G/112G/224G PAM4 links, develop SI models (IBIS, S-parameters), and correlate results with measurements to drive robust high-speed