Senior SerDes Verification Engineer (UCIe/PCIe)

Advanced Micro Devices (S) Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AMD Singapore is seeking a SerDes Verification Engineer to verify high‑speed SerDes interfaces, evaluate signal integrity, and ensure protocol compliance with UCIe/PCIe/Ethernet/USB and DDR protocols. You will develop testbenches, run simulations, and collaborate with design, RTL and firmware teams across sites.

You will use UVM and SystemVerilog to build robust verification environments, analyze results, and drive automation for regression testing.

Qualifications

• Experience in SerDes verification or high-speed communication verification.
• Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other verification tools.
• Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.
• Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.
• Solid understanding of SerDes architectures, link training, and equalization.
• Strong debugging skills across timing, protocol, and performance domains.
• Familiarity with HDL like VHDL or Verilog.
• Experience with DDR protocol (e.g., DDR3/4/5) for memory interface verification.
• Understanding of UCIe protocol and chiplet-to-chiplet communication.
• Experience with Python, Perl, or similar scripting languages for automation.
• Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
• Ability to work in fast-paced environment and manage multiple verification tasks.

Responsibilities

• Verify SerDes designs and develop verification plans and testbenches to meet functional/performance goals.
• Write and drive formal verification properties and assertions for blocks.
• Develop directed and random verification tests and assess coverage.
• Design and implement verification testbenches using UVM/SystemVerilog/VHDL.
• Run simulations, analyze results, and debug timing/protocol issues in SerDes blocks.
• Evaluate jitter, BER, eye diagrams, and signal integrity in verification.
• Ensure protocol compliance with UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, etc.
• Create automated regression tests for stability across versions.
• Collaborate with design, RTL/firmware teams and document results.

Skills

SerDes verification

UVM

SystemVerilog

HDL (Verilog/VHDL)

Signal integrity

PCIe/UCIe protocols

Debugging

DDR protocols

Python/Perl

Education

Bachelors or Masters in Computer/Electrical Engineering

Tools

UVM

SystemVerilog

Verilog/VHDL

Python scripting

Job description

AMD Singapore is seeking a SerDes Verification Engineer to verify high‑speed SerDes interfaces, evaluate signal integrity, and ensure protocol compliance with UCIe/PCIe/Ethernet/USB and DDR protocols. You will develop testbenches, run simulations, and collaborate with design, RTL and firmware teams across sites.

You will use UVM and SystemVerilog to build robust verification environments, analyze results, and drive automation for regression testing.