Senior SerDes Verification Engineer — UVM & PCIe expert

Advanced Micro Devices, Inc.; Singapore; On-site; SGD 110,000 - 190,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD in Singapore is seeking a SerDes Verification Engineer to verify high-speed SerDes interfaces, focusing on signal integrity, timing, and protocol compliance. You will develop and run testbenches, perform simulations, and work with RTL, hardware, and firmware teams across time zones.

You will drive formal verification, debug failures, and build automated regression tests to ensure robustness across multiple silicon iterations. Strong HDL and scripting skills are essential for success.

Qualifications

• Experience in SerDes verification or high-speed communication verification.
• Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.
• Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.
• Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.
• Solid understanding of SerDes architectures, link training, and equalization.
• Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
• Familiarity with HDL languages like VHDL or Verilog.
• Strong analytical, problem-solving, and communication skills.
• Experience with DDR protocol (DDR3/DDR4/DDR5) for memory interface verification.
• Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.
• Experience with Python, Perl, or similar scripting languages for automation.

Responsibilities

• Verification of SerDes designs across IPs and subsystems to meet functional and performance requirements.
• Develop testbenches and drive formal verification; write properties and assertions.
• Design verification tests and estimate test coverage and required changes to test env.
• Create verification testbenches using UVM/SystemVerilog/VHDL.
• Run simulations, analyze results, and debug timing and protocol issues in SerDes blocks.
• Evaluate performance metrics: jitter, BER, eye diagrams, signal integrity.
• Test protocol compliance for UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, etc.
• Develop automated regression tests for multiple design versions.
• Collaborate with RTL, hardware, and firmware teams; document results.

Skills

UVM

SystemVerilog

SerDes verification

Signal integrity

Debugging

Python scripting

DDR protocols

PCIe

UCIe

HDL Verilog/VHDL

Education

Bachelors or Masters in Computer Engineering/Electrical Engineering

Tools

Verilog

VHDL

UVM environment tools

Job description

AMD in Singapore is seeking a SerDes Verification Engineer to verify high-speed SerDes interfaces, focusing on signal integrity, timing, and protocol compliance. You will develop and run testbenches, perform simulations, and work with RTL, hardware, and firmware teams across time zones.

You will drive formal verification, debug failures, and build automated regression tests to ensure robustness across multiple silicon iterations. Strong HDL and scripting skills are essential for success.