Physical Design Engineer - Physical Verification - Singapore

ByteDance; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

ByteDance's Silicon Platform Team is seeking a Senior PV Engineer to own PV signoff for advanced-node ASIC/SoC designs. You will lead PV methodology, collaborate with Foundry/EDA vendors, and drive early PDK validation and signoff closure.

You should have 5+ years in physical verification, hands-on PV tool experience, and a strong ability to troubleshoot PV issues across teams. Regular Singapore-based role with cross-functional exposure.

Qualifications

• BS degree in Electrical or Computer Engineering or equivalent practical experience.
• 5+ years of physical verification experience for ASIC/SoC designs.
• Hands-on experience with PV tools and PV signoff flow.

Responsibilities

• Own and drive PV signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC checks.
• Manage the PV flow from PDK enablement through tapeout and signoff closure.
• Collaborate with Foundry and EDA vendors on rule-deck bring-up and issue resolution.
• Perform in-depth PV result analysis and regression across PV tool versions.
• Interface between the company and Foundry/PDK teams, tracking issues and validating fixes.

Skills

PV expertise

Team collaboration

Communication skills

Education

BS in Electrical Engineering or equivalent

Tools

Mentor Calibre

Synopsys IC Validator

Job description

Join us as we work together to inspire creativity and enrich life around the globe.

Location:

Team:

Technology

Employment Type:

Regular

Job Code:

A70775A

Share this listing:

Responsibilities

Team IntroductionThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape‑out, mass production, packaging, testing, and board‑level verification. They collaborate closely with front‑end chip teams across business units to drive R&D progress and mass production deployment for chip.

1. Own and drive Physical Verification (PV) signoff for advanced‑node ASIC/SoC designs, including DRC/LVS/ERC/ANT, fill program, ESD PERC/Reliability checks, GDS scramble, and advanced package related verification.
2. Own the complete PV flow from early PDK test/enablement through final tapeout, including PV methodology development, flow bring‑up, debugging, and signoff closure.
3. Drive early PDK and rule‑deck bring‑up and validation. For immature or early‑release PDKs/verification decks: analyze PV results, identify root cause (design/PDK/rule deck/technology file/tool), develop focused test cases, and work with Foundry and EDA vendors to drive closure.
4. Perform in‑depth PV result analysis and debugging, including hierarchical/flat run monitoring, IP verification and SoC‑level integration, regression analysis across rule‑deck/PDK versions, and PV‑PR correlation.
5. Act as the technical interface between the company and Foundry/PDK teams/EDA vendors, including issue reporting and tracking, test case preparation, rule interpretation discussion, and rule‑deck fix validation.
6. Develop and maintain PV signoff methodology, including checklists, run strategies, waiver methodology, regression methodology, and signoff criteria.

Qualifications

Minimum Qualifications

1. BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
2. 5+ years of experience in physical verification (DRC/LVS/ERC) for ASIC/SoC designs.
3. Hands‑on experience with industry‑standard PV tools (e.g., Mentor Calibre, Synopsys IC Validator).
4. Experience with PV signoff flow from PDK enablement through tapeout.
5. Experience working with Foundry and EDA vendors on rule‑deck bring‑up and issue resolution.

Preferred Qualifications

1. Experience with 7nm/5nm/3nm/2nm or other advanced nodes.
2. Experience with early PDK bring‑up and immature rule‑deck validation.
3. Experience with advanced package related PV verification.
4. Experience developing PV methodology, including waiver and regression frameworks.

Job Information

About Us

Why Join ByteDance

Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.

As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.

Diversity & Inclusion

ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.