SoC Physical Design Engineer — Full-Chip Tapeout Lead

ByteDance; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

ByteDance's Silicon Platform Team in Singapore leads R&D for chip development, covering logic to tapeout, DFT, and power/EM/IR studies. You will own full chip/SoC physical implementation from planning to GDS/tapeout, shaping floorplanning, clock architecture, and hierarchical design.

Collaborate with front-end teams to bring mass production to life. The role requires 5+ years in physical design, hands-on PD tooling, and strong collaboration across disciplines to deliver high-quality silicon on

Qualifications

• BS degree in Electrical or Computer Engineering or equivalent.
• 5+ years of experience in physical design / physical implementation.
• Experience owning full chip / SoC physical implementation from planning to tapeout.
• Hands-on experience with PD tools incl. Synopsys ICC2 and Cadence Innovus.
• Experience with chip-level floorplanning, clock architecture and hierarchical methods.

Responsibilities

• Own the full chip / SoC from early physical planning through final GDS/tapeout.
• Define chip-level physical design strategy and floorplanning targets.
• Drive partitioning, pin/bump planning and clock architecture design.
• Establish hierarchical implementation methodology.
• Drive convergence across all physical-design blocks and subsystems.

Skills

Physical design

SoC implementation

Floorplanning

Clock architecture

Hierarchical methodology

Education

BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience

Tools

Synopsys ICC2

Cadence Innovus

Job description

ByteDance's Silicon Platform Team in Singapore leads R&D for chip development, covering logic to tapeout, DFT, and power/EM/IR studies. You will own full chip/SoC physical implementation from planning to GDS/tapeout, shaping floorplanning, clock architecture, and hierarchical design.

Collaborate with front-end teams to bring mass production to life. The role requires 5+ years in physical design, hands-on PD tooling, and strong collaboration across disciplines to deliver high-quality silicon on