Senior PCIe IP Design Engineer (Verilog RTL)

BITDEER DEVELOPMENT PTE. LTD.; Singapore; Sur place; SGD 90 000 - 130 000; Plein temps

Résumé du poste

Bitdeer Development Pte. Ltd. in Singapore is seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe IP blocks and support verification closure.

The role involves ensuring functional coverage and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions. Responsibilities include supporting pre-silicon and post-silicon debugging, contributing to design verification, and assisting software development.

Qualifications

• Requires Verilog RTL development experience for PCIe IP blocks.
• Strong understanding of PCIe architecture and logic design.
• Proven debugging skills and problem-solving abilities.
• Scripting proficiency (Perl, Shell, TCL) to automate tasks.

Responsabilités

• Implement Verilog RTL for PCIe IP blocks.
• Support verification closure and ensure functional coverage.
• Contribute to pre-silicon and post-silicon debugging across cores.
• Collaborate with verification and software teams to deliver robust IP.

Connaissances

Verilog RTL development

PCIe architecture

Debugging skills

Scripting (Perl, Shell, TCL)

Formation

Master’s or Bachelor’s in Electrical/Computer Engineering

Bachelor’s in Electrical/Computer Engineering

Outils

Industry-standard EDA tools

Description du poste

Bitdeer Development Pte. Ltd. in Singapore is seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe IP blocks and support verification closure.

The role involves ensuring functional coverage and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions. Responsibilities include supporting pre-silicon and post-silicon debugging, contributing to design verification, and assisting software development.