Senior Front-End Engineer

BITDEER DEVELOPMENT PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Bitdeer Development Pte. Ltd. in Singapore is seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe IP blocks and support verification closure.

The role involves ensuring functional coverage and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions. Responsibilities include supporting pre-silicon and post-silicon debugging, contributing to design verification, and assisting software development.

Qualifications

• Requires Verilog RTL development experience for PCIe IP blocks.
• Strong understanding of PCIe architecture and logic design.
• Proven debugging skills and problem-solving abilities.
• Scripting proficiency (Perl, Shell, TCL) to automate tasks.

Responsibilities

• Implement Verilog RTL for PCIe IP blocks.
• Support verification closure and ensure functional coverage.
• Contribute to pre-silicon and post-silicon debugging across cores.
• Collaborate with verification and software teams to deliver robust IP.

Skills

Verilog RTL development

PCIe architecture

Debugging skills

Scripting (Perl, Shell, TCL)

Education

Master’s or Bachelor’s in Electrical/Computer Engineering

Bachelor’s in Electrical/Computer Engineering

Tools

Industry-standard EDA tools

Job description

About Bitdeer:

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

Job Summary:

We are seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe-related IP blocks and support verification closure. The role involves ensuring functional coverage, contributing to pre-silicon and post-silicon debug activities, and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions.

What you will be responsible for:

• Implement Verilog RTL for various sections of IPs, especially PCIe
• Support in verification closure by ensuring 100% coverage functionality architecture and microarchitecture of next-generation high-performance cores.
• Contribute to design verification and assist in debugging issues across pre-silicon and post-silicon stages.
• Support software development.

How you will stand out:

• Master’s degree (preferred) or Bachelor’s degree in Electrical Engineering, or Computer Engineering, with 5 years or more in a semiconductor or high technology R&D experience would be appreciated.
• Verilog RTL development experience with industry-standard tools in an SoC/IP environment.
• Strong understanding of PCIe architecture and logic design.
• Strong problem-solving and debugging skills.
• Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.