Senior RTL Front-End Engineer for ASIC/SoC Design

Bitdeer (NASDAQ: BTDR); Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Welfare benefits

Training & mentoring

Job summary

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud based in Singapore. We are seeking an experienced RTL designer to contribute to ASIC design and tape-out readiness.

You will participate in architecture discussions, implement Verilog RTL, and collaborate with verification, synthesis, and timing teams to ensure design quality and on-time delivery. The role offers growth in a fast-moving startup culture with exposure to GPGPU/NPU/CPU module design.

Qualifications

• Bachelor's or master's degree in Electrical/Computer Engineering or Computer Science required.
• 3+ to 5+ years RTL design on ASIC with tape-out experience.
• Familiar with industrial standard RTL design and delivery flow.

Responsibilities

• Participated in the architectural design discussions.
• Microarchitectural design and implementation using Verilog HDL based on the architectural specifications.
• Design reviews and delivery quality control.
• Soft and hard IP identification, selection and integration
• Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on synthesis, timing and power

Skills

RTL design

Computer architecture

VLSI design

GPGPU/NPU/CPU module design

Education

Bachelors/Masters in EE/CE/CS

Job description

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud based in Singapore. We are seeking an experienced RTL designer to contribute to ASIC design and tape-out readiness.

You will participate in architecture discussions, implement Verilog RTL, and collaborate with verification, synthesis, and timing teams to ensure design quality and on-time delivery. The role offers growth in a fast-moving startup culture with exposure to GPGPU/NPU/CPU module design.