Senior Memory Packaging Pathfinding Architect

Micron Technology; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Micron Technology in Singapore seeks a Package Pathfinding Architect to shape next‑generation memory packaging and system architectures. You will drive end‑to‑end optimization across silicon, package, and board, interfacing with customers to craft scalable, high‑performance solutions for edge‑AI and datacenter memory.

The role combines deep expertise in memory timing, signaling, PDN design, and AI-enabled design automation to push the boundaries of packaging technology.

Qualifications

• Master’s degree or equivalent in EE, CE, CS or related field with industry experience.
• At least 5 years in package design, electrical simulations and tools like Ansys, Siemens and Cadence.
• Experience in memory systems package design, signaling, IO design, PDN design.

Responsibilities

• Define next-generation package pathfinding and system architectures for speed, bandwidth, power, and thermal performance.
• Lead cross-stack co-optimization across silicon, package, board, and system with package-centric solutions.
• Drive long-term memory packaging strategy and influence industry standards.
• Work with silicon and system design teams and customers for next generation and disruptive solutions to boost speed for edge‑AI and data-center memory products.
• Serve as a technical interface to internal partners, customers, and senior leaders.
• Develop AI-based EDA and automation toolsets to enhance design cycle efficiency.

Skills

Memory timing

Memory package design

Signal integrity

Power integrity

EDA tools

Data analysis tools

AI for engineering

Education

Master’s degree in EE/CE/CS

PhD in a related field

Tools

Ansys

Siemens

Cadence

Job description

Micron Technology in Singapore seeks a Package Pathfinding Architect to shape next‑generation memory packaging and system architectures. You will drive end‑to‑end optimization across silicon, package, and board, interfacing with customers to craft scalable, high‑performance solutions for edge‑AI and datacenter memory.

The role combines deep expertise in memory timing, signaling, PDN design, and AI-enabled design automation to push the boundaries of packaging technology.