Senior IC Design Engineer - RTL to GDS, 7/5/3/2nm

Broadcom; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom Singapore is seeking an experienced IC Design Engineer to design and implement 400–800 million gate ICs across 7nm/5nm/3nm/2nm nodes. You will handle RTL to GDS flows, including placement, clock tree synthesis, routing, and verification.

The role requires hands-on expertise with EDA tools, UNIX/Linux scripting, and a strong background in electrical/electronics engineering. A 5+ year track record in advanced semiconductor design is expected.

Qualifications

• Bachelor/Master/PhD in Electrical/Electronics/Computer Engineering or related field.
• Minimum 5 years of relevant experience in advanced IC design.

Responsibilities

• Design and implement 400–800M gate ICs in 7nm/5nm/3nm/2nm nodes using commercial and in-house EDA tools.
• Manage full RTL-to-GDS flow including placement, clock tree synthesis, routing, physical verification, formal verification and timing analysis.
• Contribute knowledge of front-end design and synthesis; work with UNIX/Linux scripting to automate flows.

Skills

EDA tools

RTL to GDS flow

UNIX/Linux

Scripting (tcl, bash, python)

Education

Electrical/Electronics/Computer Engineering degree or higher

Tools

Synopsys

Cadence

Siemens

Job description

Broadcom Singapore is seeking an experienced IC Design Engineer to design and implement 400–800 million gate ICs across 7nm/5nm/3nm/2nm nodes. You will handle RTL to GDS flows, including placement, clock tree synthesis, routing, and verification.

The role requires hands-on expertise with EDA tools, UNIX/Linux scripting, and a strong background in electrical/electronics engineering. A 5+ year track record in advanced semiconductor design is expected.