Senior ASIC Physical Design Engineer — RTL to GDS, 7nm–2nm

Broadcom, Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom, Inc. in Singapore is seeking an experienced hardware design engineer to lead the RTL-to-GDS flow for advanced ICs across 7nm/5nm/3nm/2nm nodes. You will work with commercial and in-house EDA tools to implement large-scale designs, performing synthesis, placement, routing, and verification.

The role requires a degree in Electrical/Electronics/Computer Engineering with 8+ years in a related field. Broadcom emphasizes equal opportunity employment and global collaboration across teams.

Qualifications

• Degree, Masters or PhD in Electrical/Electronics/Computer engineering required.
• Minimum of 8 years of experience in a relevant field.
• Broadcom is an equal opportunity employer.

Responsibilities

• Design and implement 100–400 million gate ICs in 7nm/5nm/3nm/2nm process technologies.
• Perform RTL to GDS flows including RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis.

Skills

RTL to GDS flow

EDA tools usage

UNIX/Linux

Scripting languages

GPU/CPU/DSP architecture

Education

Electrical/Electronics/Computer Engineering degree

Tools

Synopsys

Cadence

Siemens

Job description

Broadcom, Inc. in Singapore is seeking an experienced hardware design engineer to lead the RTL-to-GDS flow for advanced ICs across 7nm/5nm/3nm/2nm nodes. You will work with commercial and in-house EDA tools to implement large-scale designs, performing synthesis, placement, routing, and verification.

The role requires a degree in Electrical/Electronics/Computer Engineering with 8+ years in a related field. Broadcom emphasizes equal opportunity employment and global collaboration across teams.