Senior ASIC Physical Design Engineer RTL to GDS 7nm/5nm/3nm

Broadcom, Inc.; Singapore; On-site; SGD 150,000 - 240,000; Full time

Job summary

Broadcom, Inc. is seeking a senior IC designer to lead the design and implementation of large-scale gate ICs in 7nm–2nm nodes.

You will work with Synopsys, Cadence and Siemens tools on RTL to GDS flows, including synthesis, placement, routing, and timing analysis, leveraging expertise in GPU/CPU/DSP architectures. The role requires a PhD/Masters or a strong Bachelor’s in Electrical/Electronics/Computer Engineering and 8+ years of experience.

Qualifications

• Degree or higher in Electrical/Electronics/Computer Engineering.
• Minimum 8+ years of relevant experience.
• Experience with RTL to GDS workflows and EDA tools.

Responsibilities

• Design and implement 100–400 million gate ICs in 7nm/5nm/3nm/2nm nodes.
• Perform RTL synthesis, placement, clock tree synthesis, detailed routing and verification.
• Conduct timing, formal verification and physical verification checks.

Skills

EDA tools

Unix/Linux

Scripting

GPU/CPU/DSP

RTL to GDS

Education

Electrical/Electronics/Computer Eng (Degree or higher)

Tools

Synopsys

Cadence

Siemens

Job description

Broadcom, Inc. is seeking a senior IC designer to lead the design and implementation of large-scale gate ICs in 7nm–2nm nodes.

You will work with Synopsys, Cadence and Siemens tools on RTL to GDS flows, including synthesis, placement, routing, and timing analysis, leveraging expertise in GPU/CPU/DSP architectures. The role requires a PhD/Masters or a strong Bachelor’s in Electrical/Electronics/Computer Engineering and 8+ years of experience.