Senior Engineer - IC Design

future technology devices international limited singapore branch; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

future technology devices international limited singapore branch is seeking a Digital IC Design engineer in Singapore with 5+ years of experience to drive RTL design, timing analysis, DFT tasks, and FPGA verification. The role requires collaboration with physical designers and systems teams to ensure successful tape-out and robust production testing.

The candidate will lead DFT activities, participate in design reviews, and support ISO documentation while adapting to evolving work practices.

Qualifications

• 5+ years or more experience in digital IC design.
• Design to tape-out experience is essential.
• Proficient in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure.
• Experience using EDA tools from Cadence and Synopsys.
• Knowledge of USB, UART, SPI, I2C connectivity and mixed-signal design is a plus.
• Project management skills and ability to work across teams.

Responsibilities

• Perform Verilog RTL design to meet product specifications and requirements
• Perform Logic Synthesis, Static Timing Analysis
• Work with Physical designer to achieve timing closure
• Collaborate with Systems and Software teams on FPGA verification
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Assist test teams in debugging production test issues
• Debug and correct functional issues in taped-out devices
• Participate in design reviews and support ISO processes/docs

Skills

Verilog RTL design

Logic Synthesis

Static Timing Analysis

DFT

ATPG

Timing Closure

EDA Tools Cadence

EDA Tools Synopsys

USB/UART/SPI/I2C

Project Management

Education

Degree/Master in Electrical/Electronic Engineering

Tools

Cadence

Synopsys

Job description

Digital IC Design

• Perform Verilog RTL design to meet product specifications and requirements
• Perform Logic Synthesis, Static Timing Analysis
• Work with Physical designer to achieve timing closure
• Work with Systems and Software engineers on FPGA verification
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with test team in debugging production test issues
• Help debug & correct any functional issues found in taped-out devices
• Participate in design reviews, support ISO processes and documentation

Additional Responsibilities

1. Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.
2. As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge and Skill Requirements

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in the area of digital IC design
• Working experience from design to tape-out are essential
• Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure
• Experience in using EDA tools from Cadence, Synopsys
• Knowledge and working experience in one or more of the following:
• Digital and mixed-signal design
• USB interface products
• Knowledge in connectivity technology such as USB, UART, SPI, I2C
• Project Management