Engineer (IC Design)

FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED SINGAPORE BRANCH; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED SINGAPORE BRANCH is seeking an experienced IC Physical Design Engineer to contribute to full-chip physical design development for FTDI products. You will work on tech file libraries, floor-planning, CTS, place and route, RC extraction and collaborate with front-end designers to meet timing closure.

The role requires a degree in Electrical/Electronic Engineering and 3+ years in ASIC flow layout design, with hands-on Verilog/VHDL experience and

Qualifications

• Degree or Master in Electrical/Electronic Engineering required.
• 3+ years in ASIC flow layout design with full-chip responsibilities.
• Experience from design to tape-out essential; timing closure experience preferred.

Responsibilities

• Full-chip IC physical design development for FTDI products.
• Tech file library preparation, floor-planning, CTS, place and route, RC extraction.
• Collaborate with front-end designers to achieve timing closure and optimize area/power.
• Perform physical verification (LVS/DRC/ERC/Antenna).
• Design ECO revisions and interface with foundry for tapeout activities.

Skills

Verilog HDL

VHDL design

Floor planning

Clock tree synthesis

Place and route

RC extraction

Timing ECO

Physical verification

Tapeout flow

USB connectivity

ASIC flow layout

Project management

Education

Electrical/Electronic Engineering degree

Tools

Siemens Calibre

Synopsys ICC2

Job description

Job Purpose

Performing IC Physical Design Development

Key Responsibilities

Digital IC Design

• Perform full-chip IC physical design development of products for FTDI products
• Perform tech file library preparation, full-chip floor-planning, clock tree synthesis, place and route, RC extraction
• Work with front-end designers to achieve timing closure (timing ECO) and to optimize area/power
• Perform physical verification (LVS/DRC/ERC/Antenna)
• Perform design revision (design ECO)
• Interface with foundry for tapeout-related activities

Additional Responsibilities

• Any reasonable task assigned by management and deemed to be within the individuals' capabilities to ensure smooth running of the business.
• As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Knowledge & Skill Requirements

Degree/Master in Electrical/Electronic Engineering

3 years or above experience in the area of ASIC flow layout design

Working experience from design to tape-out are essential

Experience in Verilog HDL and VHDL design, tech file library preparation, floor-planning, clock tree synthesis, place and route, RC extraction, design and timing ECO, physical verification and tapeout flow

Experience in using EDA tools from Siemens Calibre and Synopsys ICC2

Knowledge and working experience in one or more of the following:

• Digital and mixed-signal design
• USB interface products
• Knowledge in connectivity technology such as USB, UART, SPI, I2C
• Project Management

Working Conditions

• Working conditions are normal for an office environment.
• Work requires willingness to work a flexible schedule.